Daniel Cederman 7faf1a0868
[Sparc] Add errata workaround pass for GR712RC and UT700 (#103843)
This patch adds a pass that provides workarounds for the errata
described in GRLIB-TN-0009, GRLIB-TN-0010, GRLIB-TN-0011, GRLIB-TN-0012,
and GRLIB-TN-0013, that are applicable to the GR712RC and UT700. The
documents are available for download from here:

https://www.gaisler.com/index.php/information/app-tech-notes

The pass will detect certain sensitive instruction sequences and prevent
them from occurring by inserting NOP instruction. Below is an overview
of each of the workarounds. A similar implementation is available in
GCC.

GRLIB-TN-0009:

* Insert NOPs to prevent the sequence (stb/sth/st/stf) -> (single
non-store/load instruction) -> (any store)

* Insert NOPs to prevent the sequence (std/stdf) -> (any store)

GRLIB-TN-0010:

* Insert a NOP between load instruction and atomic instruction (swap and
casa).

* Insert a NOP at branch target if load in delay slot and atomic
instruction at branch target.

* Do not allow functions to begin with atomic instruction.

GRLIB-TN-0011:

* Insert .p2align 4 before atomic instructions (swap and casa).

GRLIB-TN-0012:

* Place a NOP at the branch target of an integer branch if it is a
floating-point operation or a floating-point branch.

GRLIB-TN-0013:

* Prevent (div/sqrt) instructions in the delay slot.

* Insert NOPs to prevent the sequence (div/sqrt) -> (two or three
floating point operations or loads) -> (div/sqrt).

* Do not insert NOPs if any of the floating point operations have a
dependency on the destination register of the first (div/sqrt).

* Do not insert NOPs if one of the floating point operations is a
(div/sqrt).

* Insert NOPs to prevent (div/sqrt) followed by a branch.
2024-08-19 07:59:58 +02:00

110 lines
3.3 KiB
C++

//===------- LeonPasses.h - Define passes specific to LEON ----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
#define LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
#include "llvm/CodeGen/MachineFunctionPass.h"
namespace llvm {
class SparcSubtarget;
class LLVM_LIBRARY_VISIBILITY LEONMachineFunctionPass
: public MachineFunctionPass {
protected:
const SparcSubtarget *Subtarget = nullptr;
const int LAST_OPERAND = -1;
// this vector holds free registers that we allocate in groups for some of the
// LEON passes
std::vector<int> UsedRegisters;
protected:
LEONMachineFunctionPass(char &ID);
void clearUsedRegisterList() { UsedRegisters.clear(); }
void markRegisterUsed(int registerIndex) {
UsedRegisters.push_back(registerIndex);
}
};
class LLVM_LIBRARY_VISIBILITY ErrataWorkaround : public MachineFunctionPass {
protected:
const SparcSubtarget *ST;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
bool checkSeqTN0009A(MachineBasicBlock::iterator I);
bool checkSeqTN0009B(MachineBasicBlock::iterator I);
bool checkSeqTN0010First(MachineBasicBlock &MBB);
bool checkSeqTN0010(MachineBasicBlock::iterator I);
bool checkSeqTN0012(MachineBasicBlock::iterator I);
bool checkSeqTN0013(MachineBasicBlock::iterator I);
bool moveNext(MachineBasicBlock::iterator &I);
bool isFloat(MachineBasicBlock::iterator I);
bool isDivSqrt(MachineBasicBlock::iterator I);
void insertNop(MachineBasicBlock::iterator I);
public:
static char ID;
ErrataWorkaround();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override { return "Errata workaround pass"; };
};
class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
public:
static char ID;
InsertNOPLoad();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after "
"every single-cycle load instruction when the next instruction is "
"another load/store instruction";
}
};
class LLVM_LIBRARY_VISIBILITY DetectRoundChange
: public LEONMachineFunctionPass {
public:
static char ID;
DetectRoundChange();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "DetectRoundChange: Leon erratum detection: detect any rounding "
"mode change request: use only the round-to-nearest rounding mode";
}
};
class LLVM_LIBRARY_VISIBILITY FixAllFDIVSQRT : public LEONMachineFunctionPass {
public:
static char ID;
FixAllFDIVSQRT();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "
"instructions with NOPs and floating-point store";
}
};
} // namespace llvm
#endif // LLVM_LIB_TARGET_SPARC_LEON_PASSES_H