17bfc00f7c
As discussed in [1], introduce BPF instructions with load-acquire and
store-release semantics under -mcpu=v4. Define 2 new flags:
BPF_LOAD_ACQ 0x100
BPF_STORE_REL 0x110
A "load-acquire" is a BPF_STX | BPF_ATOMIC instruction with the 'imm'
field set to BPF_LOAD_ACQ (0x100).
Similarly, a "store-release" is a BPF_STX | BPF_ATOMIC instruction with
the 'imm' field set to BPF_STORE_REL (0x110).
Unlike existing atomic read-modify-write operations that only support
BPF_W (32-bit) and BPF_DW (64-bit) size modifiers, load-acquires and
store-releases also support BPF_B (8-bit) and BPF_H (16-bit). An 8- or
16-bit load-acquire zero-extends the value before writing it to a 32-bit
register, just like ARM64 instruction LDAPRH and friends.
As an example (assuming little-endian):
long foo(long *ptr) {
return __atomic_load_n(ptr, __ATOMIC_ACQUIRE);
}
foo() can be compiled to:
db 10 00 00 00 01 00 00 r0 = load_acquire((u64 *)(r1 + 0x0))
95 00 00 00 00 00 00 00 exit
opcode (0xdb): BPF_ATOMIC | BPF_DW | BPF_STX
imm (0x00000100): BPF_LOAD_ACQ
Similarly:
void bar(short *ptr, short val) {
__atomic_store_n(ptr, val, __ATOMIC_RELEASE);
}
bar() can be compiled to:
cb 21 00 00 10 01 00 00 store_release((u16 *)(r1 + 0x0), w2)
95 00 00 00 00 00 00 00 exit
opcode (0xcb): BPF_ATOMIC | BPF_H | BPF_STX
imm (0x00000110): BPF_STORE_REL
Inline assembly is also supported.
Add a pre-defined macro, __BPF_FEATURE_LOAD_ACQ_STORE_REL, to let
developers detect this new feature. It can also be disabled using a new
llc option, -disable-load-acq-store-rel.
Using __ATOMIC_RELAXED for __atomic_store{,_n}() will generate a "plain"
store (BPF_MEM | BPF_STX) instruction:
void foo(short *ptr, short val) {
__atomic_store_n(ptr, val, __ATOMIC_RELAXED);
}
6b 21 00 00 00 00 00 00 *(u16 *)(r1 + 0x0) = w2
95 00 00 00 00 00 00 00 exit
Similarly, using __ATOMIC_RELAXED for __atomic_load{,_n}() will generate
a zero-extending, "plain" load (BPF_MEM | BPF_LDX) instruction:
int foo(char *ptr) {
return __atomic_load_n(ptr, __ATOMIC_RELAXED);
}
71 11 00 00 00 00 00 00 w1 = *(u8 *)(r1 + 0x0)
bc 10 08 00 00 00 00 00 w0 = (s8)w1
95 00 00 00 00 00 00 00 exit
Currently __ATOMIC_CONSUME is an alias for __ATOMIC_ACQUIRE. Using
__ATOMIC_SEQ_CST ("sequentially consistent") is not supported yet and
will cause an error:
$ clang --target=bpf -mcpu=v4 -c bar.c > /dev/null
bar.c:1:5: error: sequentially consistent (seq_cst) atomic load/store is
not supported
1 | int foo(int *ptr) { return __atomic_load_n(ptr, __ATOMIC_SEQ_CST); }
| ^
...
Finally, rename those isST*() and isLD*() helper functions in
BPFMISimplifyPatchable.cpp based on what the instructions actually do,
rather than their instruction class.
[1]
https://lore.kernel.org/all/20240729183246.4110549-1-yepeilin@google.com/
122 lines
4.0 KiB
C++
122 lines
4.0 KiB
C++
//===-- BPFSubtarget.h - Define Subtarget for the BPF -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the BPF specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_BPF_BPFSUBTARGET_H
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#define LLVM_LIB_TARGET_BPF_BPFSUBTARGET_H
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#include "BPFFrameLowering.h"
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#include "BPFISelLowering.h"
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#include "BPFInstrInfo.h"
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#include "BPFRegisterInfo.h"
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#include "BPFSelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "BPFGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class BPFSubtarget : public BPFGenSubtargetInfo {
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virtual void anchor();
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BPFInstrInfo InstrInfo;
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BPFFrameLowering FrameLowering;
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BPFTargetLowering TLInfo;
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BPFSelectionDAGInfo TSInfo;
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private:
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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protected:
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// unused
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bool isDummyMode;
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bool IsLittleEndian;
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// whether the cpu supports jmp ext
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bool HasJmpExt;
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// whether the cpu supports jmp32 ext.
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// NOTE: jmp32 is not enabled when alu32 enabled.
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bool HasJmp32;
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// whether the cpu supports alu32 instructions.
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bool HasAlu32;
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// whether we should enable MCAsmInfo DwarfUsesRelocationsAcrossSections
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bool UseDwarfRIS;
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// whether cpu v4 insns are enabled.
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bool HasLdsx, HasMovsx, HasBswap, HasSdivSmod, HasGotol, HasStoreImm,
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HasLoadAcqStoreRel;
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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public:
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// This constructor initializes the data members to match that
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// of the specified triple.
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BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
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const TargetMachine &TM);
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BPFSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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// ParseSubtargetFeatures - Parses features string setting specified
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// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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bool getHasJmpExt() const { return HasJmpExt; }
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bool getHasJmp32() const { return HasJmp32; }
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bool getHasAlu32() const { return HasAlu32; }
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bool getUseDwarfRIS() const { return UseDwarfRIS; }
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bool hasLdsx() const { return HasLdsx; }
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bool hasMovsx() const { return HasMovsx; }
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bool hasBswap() const { return HasBswap; }
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bool hasSdivSmod() const { return HasSdivSmod; }
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bool hasGotol() const { return HasGotol; }
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bool hasStoreImm() const { return HasStoreImm; }
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bool hasLoadAcqStoreRel() const { return HasLoadAcqStoreRel; }
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bool isLittleEndian() const { return IsLittleEndian; }
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const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const BPFFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const BPFTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const BPFSelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const BPFRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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};
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} // End llvm namespace
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#endif
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