Philip Reames 8eb4ada181

[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available (#142036) ...

If we have the ri.vinsert/vextract instructions from xrivosvisni, we can
do an element insert or extract without needing a vslide or a vector
temporary register. Adjust the TTI cost to reflect this.

2025-05-30 11:06:28 -07:00

..

AArch64

[AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (#140062)

2025-05-27 11:21:57 +01:00

AMDGPU

[AMDGPU] Update cost model gfx950 min/max tests. NFC. (#139310)

2025-05-09 13:04:06 -07:00

ARM

[ARM] Do not assume memory intrinsics specify alignment. (#138356)

2025-05-07 16:25:03 +01:00

NVPTX

[NVPTX] Improve modeling of inline PTX (#130675)

2025-03-25 13:46:16 -07:00

PowerPC

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RISCV

[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available (#142036)

2025-05-30 11:06:28 -07:00

SystemZ

Fix regression tests with bad FileCheck checks (#140373)

2025-05-22 07:59:57 +03:00

X86

[TTI] Provide a cost for memset_pattern which matches the libcall (#139978)

2025-05-28 09:39:55 -07:00

free-intrinsics-datalayout.ll

[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)

2025-04-01 14:27:11 +01:00

free-intrinsics-no_info.ll

[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)

2025-04-01 14:27:11 +01:00

no_info.ll

…