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llvm-project/llvm/test/CodeGen
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Caroline Concatto 73e4e9cd00 [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 
This patch implements vector_splice in tablegen for:
  a) when the immediate is equal to -1 (Imm==1) and uses:
       INSR  +  LASTB
For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, -1)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <D, E, F, G>
    LAST   RegLast, Vector_1                 // RegLast = D
    INSR   Res, (Vector_1 >> 1), RegLast     // Res = D + E, F, G

Differential Revision: https://reviews.llvm.org/D105633
2021-07-26 11:25:01 +01:00
..
AArch64
[AArch64][SVE] Improve code generation for vector_splice for Imm == -1
2021-07-26 11:25:01 +01:00
AMDGPU
Revert rG939291041bb35b8088e3b61be2b8b3bc950f64a7 "[AMDGPU] Regenerate wave32.ll test checks"
2021-07-25 15:59:26 +01:00
ARC
…
ARM
ARM: don't return by popping PC if we have to adjust the stack afterwards.
2021-07-21 09:35:14 +01:00
AVR
[AVR] Only support sp, r0 and r1 in llvm.read_register
2021-07-24 14:03:27 +02:00
BPF
[BPF] Use elementtype attribute for preserve.array/struct.index intrinsics
2021-07-17 11:09:18 +02:00
Generic
[llc] Default MCUseDwarfDirectory to true
2021-07-12 17:44:02 -07:00
Hexagon
[DAG] Reassociate Add with Or
2021-07-07 10:21:07 +01:00
Inputs
…
Lanai
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
M68k
[M68k][GloballSel] LegalizerInfo implementation
2021-07-15 13:00:43 -06:00
Mips
[llvm][sve] Lowering for VLS truncating stores
2021-07-23 14:04:55 +01:00
MIR
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
MSP430
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
NVPTX
[NVPTX] Add select(cc,binop(),binop()) fast-math tests
2021-07-18 15:30:24 +01:00
PowerPC
[PowerPC] Implement XL compatible behavior of __compare_and_swap
2021-07-23 01:16:02 +00:00
RISCV
[SelectionDAG] Support scalable-vector splats in yet more cases
2021-07-26 10:15:08 +01:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
[SystemZ] Handle NoRegister in SystemZTargetLowering::emitMemMemWrapper().
2021-07-19 20:04:44 +02:00
Thumb
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
Thumb2
[ARM] Extend more reductions during lowering
2021-07-19 08:58:03 +01:00
VE
[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.
2021-06-29 11:00:11 -07:00
WebAssembly
[WebAssembly] Codegen for pmin and pmax
2021-07-23 14:49:21 -07:00
WinCFGuard
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
WinEH
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
X86
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets
2021-07-26 11:11:56 +01:00
XCore
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00