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llvm-project/llvm/test/CodeGen/RISCV
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Craig Topper 28ab032298 [RISCV] Add isel patterns to form tail undisturbed vfwadd.wv from fpextend_vl+vfwadd_vl+vp_merge. 
We use a special TIED instructions for vfwadd.wv to avoid an
earlyclobber constraint preventing the first source and the destination
from being the same register.

This prevents our normal post process for forming TU instructions.
Add manual isel pattern instead. This matches what we do for FMA
for example.
2023-05-26 16:44:20 -07:00
..
GlobalISel
[RISCV][GlobalISel] Add lowerReturn for calling conv
2023-05-23 11:24:54 -07:00
intrinsics
…
rvv
[RISCV] Add isel patterns to form tail undisturbed vfwadd.wv from fpextend_vl+vfwadd_vl+vp_merge.
2023-05-26 16:44:20 -07:00
add-before-shl.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
add-imm.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
addc-adde-sube-subc.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
addcarry.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
addimm-mulimm.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
addrspacecast.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
aext-to-sext.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
align-loops.ll
[CodeGen] Add -align-loops
2021-08-04 12:45:18 -07:00
align.ll
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
alloca.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu8.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu16.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
alu64.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
analyze-branch.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
and.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
arith-with-overflow.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
atomic-cmpxchg-branch-on-result.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg-flag.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-fence.ll
[RISCV] Implement a proposed mapping for Ztso
2023-02-09 12:00:05 -08:00
atomic-load-store.ll
[RISCV] Implement a proposed mapping for Ztso
2023-02-09 12:00:05 -08:00
atomic-rmw.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-signext.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Add a DAG combine to fold (add (xor (setcc X, Y), 1) -1)->(neg (setcc X, Y)).
2023-04-28 16:52:55 -07:00
attributes.ll
[RISCV][test] Finish removing unneeded (implied) 'f' from Zvfbfwma, Zvfbfmin attribute tests
2023-05-22 14:38:05 +01:00
bitextract-mac.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
bitreverse-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
bittest.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
blockaddress.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
branch_zero.ll
[RISCV] Omit SRA in case of setlt or setge with zero constant
2022-12-21 14:19:49 +03:00
branch-on-zero.ll
[RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare
2023-02-28 14:43:40 +08:00
branch-relaxation.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
branch.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
bswap-bitreverse.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
bswap-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
byval.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
callee-saved-fpr32s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-fpr64s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-gprs.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
calling-conv-half.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-ilp32-ilp32f-common.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
calling-conv-ilp32.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
calling-conv-lp64-lp64f-lp64d-common.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
calling-conv-lp64.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-vector-on-stack.ll
[RISCV] Pass vector argument by stack correctly.
2023-03-15 17:22:47 +08:00
calls.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
cmp-bool.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
codemodel-lowering.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
compress-float.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
compress-inline-asm.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
compress-opt-branch.ll
[RISCV] Optimization for using compressed beqz and bnez PR#56391
2022-10-06 09:33:32 -07:00
compress-opt-select.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
compress.ll
[RISCV] Add integer scalar instructions to isAssociativeAndCommutative
2022-12-29 11:43:40 +00:00
condops.ll
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
copy-frameindex.mir
llvm-reduce: Don't assert on functions which don't track liveness
2022-06-07 10:00:25 -04:00
copyprop.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
copysign-casts.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
ctlz-cttz-ctpop.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
disable-tail-calls.ll
…
disjoint.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
div_minsize.ll
[RISCV]Enable isIntDivCheap when attribute is minsize
2022-07-27 18:22:51 +08:00
div-by-constant.ll
[RISCV] Refine the (mul (zext.w X), C) -> mulhu isel heuristic.
2023-01-28 00:05:19 -08:00
div-pow2.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
div.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
double_reduct.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
double-arith-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-arith.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-br-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-calling-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-convert-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-convert.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-frem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-imm.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-isnan.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-mem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-previous-failure.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv-sat.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-icmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-stack-spill-restore.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
dso_local_equivalent.ll
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
dwarf-eh.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.
2023-04-05 19:28:05 -07:00
early-clobber-tied-def-subreg-liveness.mir
Reland "[SplitKit] Handle early clobber + tied to def correctly"
2022-06-16 17:13:09 +08:00
eh-dwarf-cfa.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
elf-preemption.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
emutls.ll
[RISCV] Support emulated TLS
2023-03-29 20:55:51 +01:00
exception-pointer-register.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fastcc-float.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
fastcc-int.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fixups-diff.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fixups-relax-diff.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fli-licm.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
float-arith-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-arith.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bit-preserving-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-br-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-convert-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-frem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-imm.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-isnan.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-mem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv-sat.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-icmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-verify.ll
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
2023-02-03 22:42:08 -08:00
float-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
flt-rounds.ll
[Intrinsic] Rename flt.rounds intrinsic to get.rounding
2022-12-19 15:22:39 +08:00
fmax-fmin.ll
[SDAG] avoid libcalls to fmin/fmax for soft-float targets
2022-03-30 11:22:03 -04:00
fold-addi-loadstore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
forced-atomics.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
fp16-promote.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fp128.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
fp-imm.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fpclamptosat.ll
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.
2023-05-23 09:19:55 -07:00
fpenv.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
frame-info.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
frame.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
frameaddr-returnaddr.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
frm-dependency.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
get-register-reserve.ll
…
get-setcc-result-type.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
ghccc-nest.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
ghccc-rv32.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
ghccc-rv64.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
global-merge-offset.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
global-merge.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
half-arith-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-arith.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-br-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-convert-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
half-convert.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
half-fcmp-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-frem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-isnan.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-mem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-round-conv-sat.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-round-conv.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-select-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-select-icmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-zfa-fli.ll
[RISCV] Pre-commit tests for D145897. NFC
2023-03-14 13:11:11 -07:00
half-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
hoist-global-addr-base.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
hwasan-check-memaccess.ll
[RISC-V][HWASAN] Don't explicitly load GOT entry to call hwasan mismatch routine
2023-01-09 16:46:28 +03:00
i32-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
i64-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
iabs.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
imm-cse.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
imm.ll
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
2023-02-13 17:02:09 +01:00
indirectbr.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
init-array.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
2021-12-23 20:32:36 -06:00
inline-asm-S-constraint.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
inline-asm-zfh-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm.ll
[RISCV] Lower inline asm m with offset to register+imm.
2023-03-31 13:20:13 -03:00
inline-option-directive.ll
[RISCV] Support '.option arch' directive
2023-05-26 18:39:41 +08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Remove the uret instruction.
2023-04-26 17:11:58 -07:00
isel-optnone.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
jumptable.ll
Revert "[CodeGen][ShrinkWrap] Split restore point"
2023-04-13 10:52:28 +05:30
lack-of-signed-truncation-check.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
large-stack.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
legalize-fneg.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
libcall-tail-calls.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
live-sp.mir
[RISCV] Fix invalid kill on callee save
2021-11-02 11:56:54 +00:00
local-stack-slot-allocation.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions
2023-01-24 11:42:37 -08:00
lsr-legaladdimm.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
machine-combiner-mir.ll
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
2022-11-17 13:24:04 +03:00
machine-combiner-strategies.ll
[MachineCombiner] Support local strategy for traces
2023-02-17 13:17:22 +03:00
machine-combiner.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-cp.mir
[MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow.
2022-06-17 21:40:08 -07:00
machine-cse.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-outliner-and-machine-copy-propagation.ll
[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
2023-03-14 17:55:11 +00:00
machine-outliner-cfi.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-patchable.ll
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
2021-12-13 13:24:29 -08:00
machine-outliner-position.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-throw.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
machinelicm-address-pseudos.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
machineoutliner-jumptable.mir
[RISCV] Fix Machine Outliner jump table handling.
2021-09-09 07:32:30 +02:00
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel-lo operand.
2022-08-24 21:47:46 +08:00
machineoutliner.mir
[MachineOutliner] Add IsOutlined to MachineFunction
2023-04-10 10:57:29 +08:00
MachineSink-implicit-x0.mir
Fix minor deficiency in machine-sink.
2021-11-12 08:01:13 +01:00
macro-fusion-lui-addi.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
make-compressible-for-store-address.mir
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
make-compressible-rv64.mir
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
make-compressible.mir
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mem64.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
mem.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
memcpy-inline.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
min-max.ll
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.
2023-05-23 09:19:55 -07:00
mir-target-flags.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
miss-sp-restore-eh.ll
[RISCV] Fix missing stack pointer recover
2022-06-09 23:38:50 +08:00
module-target-abi2.ll
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
2022-03-24 00:48:52 +08:00
module-target-abi3.ll
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
2022-08-26 14:39:39 +08:00
module-target-abi.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mul.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
musttail-call.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
narrow-shl-cst.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
neg-abs.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
nest-register.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
nomerge.ll
[CodeGen] Fix nomerge attribute not working in tail calls.
2023-05-10 14:25:11 -04:00
nontemporal-scalable.ll
[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain
2023-04-24 20:15:14 -07:00
nontemporal.ll
[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain
2023-04-24 20:15:14 -07:00
O0-pipeline.ll
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
O3-pipeline.ll
[RISCV] Move NTLH hint emission into RISCVAsmPrinter.cpp.
2023-05-01 12:05:18 -07:00
option-nopic.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
or-is-add.ll
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
2022-12-28 19:59:42 -08:00
out-of-reach-emergency-slot.mir
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
overflow-intrinsic-optimizations.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
overflow-intrinsics.ll
[RISCV] Add special case for i32 uaddo X, -1 on RV64.
2023-04-01 18:54:03 -07:00
patchable-function-entry.ll
[AsmPrinter] Fix placement of function entry comments
2023-04-18 15:01:36 -07:00
pic-models.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr40333.ll
…
pr51206.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
pr53662.mir
[RISCV] Don't getDebugLoc for the end node of MBB iterator
2022-04-30 16:00:20 +08:00
pr55201.ll
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
2022-04-30 11:02:30 -07:00
pr56110.ll
[DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.
2022-06-19 15:50:15 -07:00
pr56457.ll
[RISCV] Optimize (brcond (seteq (and X, (1 << C)-1), 0))
2023-01-13 21:01:49 +08:00
pr58025.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58286.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58511.ll
[RISCV] Update pr58511.ll to not use mul by constant that can be converted to shift.
2023-05-20 19:08:05 -07:00
prefetch.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
rem.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
remat.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
repeated-fp-divisors.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
reserved-reg-errors.ll
…
reserved-regs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
riscv-codegenprepare-asm.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
riscv-codegenprepare.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
rotl-rotr.ll
[RISCV] Expand rotate by non-constant for XTHeadBb during lowering.
2023-05-23 16:31:22 -07:00
rv32-fuchsia.ll
[llvm] Prevent building for riscv32-unknown-fuchsia
2023-03-01 19:42:56 +00:00
rv32i-rv64i-float-double.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
rv32xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv32xtheadbb.ll
[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
2023-02-17 21:46:26 +01:00
rv32xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv32zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv32zbb-intrinsic.ll
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
2022-03-28 16:56:33 -07:00
rv32zbb-zbkb.ll
[RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant.
2022-12-29 15:10:36 -08:00
rv32zbb.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
rv32zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv32zbkb.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
rv32zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbs.ll
[RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./
2022-12-29 17:04:52 -08:00
rv32zknd-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zknh-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64-large-stack.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rv64d-double-convert-strict.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll
[RISCV] Set target-abi explicitly to reduce codegen results
2022-06-01 13:49:23 +08:00
rv64f-float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
rv64i-complex-float.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
rv64i-demanded-bits.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64i-double-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
rv64i-shift-sext.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
rv64i-single-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-w-insts-legalization.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv64xtheadbb.ll
[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
2023-02-17 21:46:26 +01:00
rv64xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv64zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv64zbb-intrinsic.ll
[RISCV] Remove support for the unratified Zbp extension.
2022-09-21 21:22:42 -07:00
rv64zbb-zbkb.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
rv64zbb.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
rv64zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv64zbkb.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
rv64zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbs.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
rv64zfh-half-convert-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfh-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-convert-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zknd-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknd-zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknh-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rve.ll
[RISCV][MC] Add support for RV64E
2023-03-23 12:32:25 +00:00
sadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
sadd_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
saverestore-scs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
saverestore.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
sdata-limit-0.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-4.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-8.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-local-sym.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
select-and.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-bare.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-binop-identity.ll
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
select-cc.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
select-const.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-constant-xor.ll
[RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
2022-12-28 15:17:41 -08:00
select-optimize-multiple.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-optimize-multiple.mir
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-or.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select.ll
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
selectcc-to-shiftand.ll
[RISCV] Match neg (and x, 1) to two shifts to improve codesize
2022-12-19 14:17:26 -08:00
setcc-logic.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
sext-zext-trunc.ll
[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB
2023-03-24 09:45:43 +08:00
sextw-removal.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
shadowcallstack.ll
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
shift-amount-mod.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shift-and.ll
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
2022-10-22 14:30:13 -07:00
shift-masked-shamt.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shifts.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shl-demanded.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
shlimm-addimm.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
short-foward-branch-opt.ll
[RISCV] Support the short-forward-branch predicated ops in RISCVSExtWRemoval.
2022-12-23 21:39:22 -08:00
shrinkwrap-jump-table.ll
[ShrinkWrap] Allow shrinkwrapping past memory accesses to jump tables
2023-05-11 11:33:18 -07:00
shrinkwrap.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
signbit-test.ll
[AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
2022-12-06 11:34:48 -05:00
signed-truncation-check.ll
[RISCV] Enable signed truncation check transforms for i8
2023-05-10 22:53:24 +08:00
sink-icmp.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
spill-fpr-scalar.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
split-offsets.ll
[RISCV] Pre-commit test case from PR62734. NFC
2023-05-16 16:07:23 -07:00
split-sp-adjust.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
split-store.ll
[RISCV] Implement isMultiStoresCheaperThanBitsMerge hook
2023-01-31 12:47:48 +00:00
split-udiv-by-constant.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
split-urem-by-constant.ll
Recommit "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant."
2022-10-24 10:08:50 -07:00
srem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
srem-seteq-illegal-types.ll
[RISCV] Use vslidedown for undef sub-sequences in generic build_vector
2023-05-03 07:52:29 -07:00
srem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
stack-folding.ll
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
stack-protector-target.ll
[RISCV] Clean up stack-protector-target test
2023-02-06 16:42:59 -08:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-realignment.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-slot-coloring.mir
[RISCV] Set how many bytes load from or store to stack slot
2023-03-10 10:14:59 +08:00
stack-slot-size.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
stack-store-check.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
subtarget-features-std-ext.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
switch-width.ll
[riscv] Add a bunch of tests exploring switch lowering
2022-05-11 13:16:31 -07:00
tagged-globals.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
tail-calls.ll
[RISCV] Permit tail call to an externally-defined function with weak linkage
2023-02-03 09:38:46 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
tls-models.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
trunc-free.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
uadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
uadd_sat.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
umulo-128-legalisation-lowering.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
unaligned-load-store.ll
[RISCV] Add tests for store merging with unaligned scalar access
2023-05-19 14:44:46 +01:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
unroll-loop-cse.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
urem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
urem-seteq-illegal-types.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
urem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
vararg.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
vector-abi.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
verify-instr.mir
…
vlenb.ll
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
2022-05-16 16:38:30 -07:00
vscale-demanded-bits.ll
SelectionDAG: Teach ComputeKnownBits about VSCALE
2023-05-26 10:48:49 -07:00
wide-mem.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
wide-scalar-shift-by-byte-multiple-legalization.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
wide-scalar-shift-legalization.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
xaluo.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
xtheadfmemidx.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
xtheadmac.ll
[RISCV] xtheadmac: fix commutativity issue for the in/out register
2023-02-17 19:45:22 +01:00
xtheadmemidx.ll
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
2023-02-24 00:17:58 +01:00
xtheadmempair.ll
[RISCV] XTHeadMemPair: Fix invalid mempair combine for types other than i32/i64
2023-02-22 19:57:37 +01:00
zbb-cmp-combine.ll
[RISCV] Combine comparison and logic ops
2022-12-23 17:10:21 +03:00
zdinx-boundary-check.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
zext-with-load-is-free.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
zfh-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zmmul.ll
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00