a2dc4e02e7
This patch enables the multi-group xnack replay mode by configuring the hardware MODE register at kernel entry. This aligns the hardware behavior with the compiler's existing multi-group s_wait_xcnt insertion logic.
55 lines
2.8 KiB
LLVM
55 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX1200 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
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define amdgpu_ps void @intrinsic_store_system_scope(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX1200-LABEL: intrinsic_store_system_scope:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: buffer_store_b32 v0, v[1:2], s[0:3], s4 idxen offen scope:SCOPE_SYS
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; GFX1200-NEXT: s_endpgm
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;
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; GFX1250-SDAG-LABEL: intrinsic_store_system_scope:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
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; GFX1250-SDAG-NEXT: buffer_store_b32 v0, v[2:3], s[0:3], s4 idxen offen scope:SCOPE_SYS
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: intrinsic_store_system_scope:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
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; GFX1250-GISEL-NEXT: buffer_store_b32 v0, v[4:5], s[0:3], s4 idxen offen scope:SCOPE_SYS
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; GFX1250-GISEL-NEXT: s_endpgm
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call void @llvm.amdgcn.struct.buffer.store.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 24)
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ret void
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}
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define amdgpu_ps void @generic_store_volatile(i32 %val, ptr addrspace(1) %out) {
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; GFX1200-LABEL: generic_store_volatile:
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; GFX1200: ; %bb.0:
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; GFX1200-NEXT: global_store_b32 v[1:2], v0, off scope:SCOPE_SYS
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; GFX1200-NEXT: s_wait_storecnt 0x0
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; GFX1200-NEXT: s_endpgm
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;
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; GFX1250-SDAG-LABEL: generic_store_volatile:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
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; GFX1250-SDAG-NEXT: global_store_b32 v[2:3], v0, off scope:SCOPE_SYS
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; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: generic_store_volatile:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2
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; GFX1250-GISEL-NEXT: global_store_b32 v[4:5], v0, off scope:SCOPE_SYS
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; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0
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; GFX1250-GISEL-NEXT: s_endpgm
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store volatile i32 %val, ptr addrspace(1) %out
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ret void
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}
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