169 lines
5.5 KiB
LLVM
169 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
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define void @vec_reduce_smin_v16i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <16 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vsrli.d $vr1, $vr0, 32
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v4i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.w $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
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; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v2i8(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.h $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
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; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1
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; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <2 x i8>, ptr %src
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%res = call i8 @llvm.vector.reduce.smin.v2i8(<2 x i8> %v)
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store i8 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v8i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <8 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v2i16(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.w $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
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; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1
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; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <2 x i16>, ptr %src
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%res = call i16 @llvm.vector.reduce.smin.v2i16(<2 x i16> %v)
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store i16 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v4i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14
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; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
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; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <4 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld.d $a0, $a0, 0
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; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
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; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1
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; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <2 x i32>, ptr %src
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%res = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %v)
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store i32 %res, ptr %dst
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ret void
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}
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define void @vec_reduce_smin_v2i64(ptr %src, ptr %dst) nounwind {
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; CHECK-LABEL: vec_reduce_smin_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1
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; CHECK-NEXT: vmin.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0
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; CHECK-NEXT: ret
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%v = load <2 x i64>, ptr %src
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%res = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v)
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store i64 %res, ptr %dst
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ret void
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}
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