Simon Pilgrim d40b7f0d5a [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses ...

If we're using shift pairs to mask, then relax the one use limit if the shift amounts are equal - we'll only be generating a single AND node.

AArch64 has a couple of regressions due to this, so I've enforced the existing one use limit inside a AArch64TargetLowering::shouldFoldConstantShiftPairToMask callback.

Part of the work to fix the regressions in D77804

Differential Revision: https://reviews.llvm.org/D125607

2022-05-17 13:40:11 +01:00

..

CMakeLists.txt

…

DAGCombiner.cpp

[DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses

2022-05-17 13:40:11 +01:00

FastISel.cpp

[FastISel] Fix load folding for registers with fixups

2022-05-16 10:25:25 +02:00

FunctionLoweringInfo.cpp

[RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64.

2022-04-11 14:38:39 -07:00

InstrEmitter.cpp

[DebugInfo][InstrRef] Avoid a crash from mixed variable location modes

2022-04-06 11:55:38 +01:00

InstrEmitter.h

[DebugInfo][InstrRef] Avoid a crash from mixed variable location modes

2022-04-06 11:55:38 +01:00

LegalizeDAG.cpp

[CodeGen] Fix ConvertNodeToLibcall for STRICT_FPOWI

2022-05-11 08:58:06 +08:00

LegalizeFloatTypes.cpp

[SDAG] avoid libcalls to fmin/fmax for soft-float targets

2022-03-30 11:22:03 -04:00

LegalizeIntegerTypes.cpp

[LegalizeTypes][VP] Add integer promotion support for vp.setcc

2022-05-13 06:25:13 +00:00

LegalizeTypes.cpp

Cleanup includes: DebugInfo & CodeGen

2022-03-12 17:26:40 +01:00

LegalizeTypes.h

[LegalizeTypes] Don't assume fshl/fshr shift amount type matches the other operands.

2022-05-07 11:44:07 -07:00

LegalizeTypesGeneric.cpp

[SelectionDAG][VP] Add splitting support for VP_MERGE

2022-01-25 10:33:23 +00:00

LegalizeVectorOps.cpp

[RISCV][VP] Add basic RVV codegen for vp.fcmp

2022-04-07 09:16:07 +01:00

LegalizeVectorTypes.cpp

[LegalizeVectorTypes] Enable WidenVecRes_SETCC work for scalable vector.

2022-05-12 02:52:43 +00:00

ResourcePriorityQueue.cpp

Cleanup includes: DebugInfo & CodeGen

2022-03-12 17:26:40 +01:00

ScheduleDAGFast.cpp

[DebugInfo][InstrRef] Avoid a crash from mixed variable location modes

2022-04-06 11:55:38 +01:00

ScheduleDAGRRList.cpp

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ScheduleDAGSDNodes.cpp

[DebugInfo][InstrRef] Avoid a crash from mixed variable location modes

2022-04-06 11:55:38 +01:00

ScheduleDAGSDNodes.h

[CodeGen] Use default member initialization (NFC)

2022-01-30 12:32:51 -08:00

ScheduleDAGVLIW.cpp

Cleanup includes: DebugInfo & CodeGen

2022-03-12 17:26:40 +01:00

SDNodeDbgValue.h

Cleanup includes: DebugInfo & CodeGen

2022-03-12 17:26:40 +01:00

SelectionDAG.cpp

[SelectionDAG] Support more VP reduction mask operation.

2022-05-17 09:14:21 +00:00

SelectionDAGAddressAnalysis.cpp

[SelectionDAG] Replace error prone index check in BaseIndexOffset::computeAliasing

2021-10-05 12:15:55 +02:00

SelectionDAGBuilder.cpp

[SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes.

2022-05-16 20:47:52 +01:00

SelectionDAGBuilder.h

[RISCV][VP] Add basic RVV codegen for vp.icmp

2022-04-06 16:51:22 +01:00

SelectionDAGDumper.cpp

Intrinsic for checking floating point class

2022-04-26 13:09:16 +07:00

SelectionDAGISel.cpp

[FastISel] Add some debug output (NFC)

2022-05-12 12:25:20 +02:00

SelectionDAGPrinter.cpp

Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"

2022-04-06 20:32:53 +03:00

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[StatepointLowering] Properly handle local and non-local relocates of the same value.

2022-05-16 17:02:34 +07:00

StatepointLowering.h

More precisely type code used for gc.relocate assertions [nfc]

2021-04-06 11:27:36 -07:00

TargetLowering.cpp

[SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes.

2022-05-16 20:47:52 +01:00