Shilei Tian 8aff59d3f4

[NFC][AMDGPU] Auto generate check lines for three test cases (#127352) ...

- `CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll`
- `CodeGen/AMDGPU/call-preserved-registers.ll`
- `CodeGen/AMDGPU/stack-realign.ll`

This is to make preparation for another PR.

2025-02-17 11:22:08 -05:00

..

AArch64

[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#127368)

2025-02-16 18:44:46 +00:00

AMDGPU

[NFC][AMDGPU] Auto generate check lines for three test cases (#127352)

2025-02-17 11:22:08 -05:00

ARC

[ARC,test] Change llc -march= to -mtriple=

2024-12-15 12:29:53 -08:00

ARM

[IR] Remove mul constant expression (#127046)

2025-02-14 09:28:57 +01:00

AVR

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

BPF

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

CSKY

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DirectX

[HLSL] Fix Root signature test error (#127261)

2025-02-14 15:39:52 -08:00

Generic

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Hexagon

[Hexagon] Explicitly truncate constant in UAddSubO (#127360)

2025-02-17 09:30:48 -06:00

Inputs

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Lanai

[test] Remove redundant -march= when target triple is specified in IR

2024-12-15 12:42:17 -08:00

LoongArch

[LoongArch] Add test for stackmaps. NFC

2025-02-13 20:58:26 +08:00

M68k

[M68k] always use movem for register spills (#106715)

2025-01-31 19:42:40 -06:00

Mips

Revert "[Mips] Support llvm.readcyclecounter intrinsic (#114953)"

2025-02-11 14:37:17 +08:00

MIR

MachineCopyPropagation: Do not remove copies preserved by regmask (#125868)

2025-02-10 12:26:33 -05:00

MLRegAlloc

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MSP430

[M68k,MSP430,test] Change llc -march= to -mtriple=

2024-12-15 10:09:30 -08:00

NVPTX

Reland "[NVPTX] Cleanup/Refactoring in NVPTX AsmPrinter and RegisterInfo (NFC)" (#127277)

2025-02-14 18:45:14 -08:00

PowerPC

[PowerPC] Use getSignedTargetConstant in SelectOptimalAddrMode. (#127305)

2025-02-15 14:13:32 -08:00

RISCV

[RISCV] Recognize de-interleave shuffles with 2 sources. (#127272)

2025-02-16 20:40:09 -08:00

SPARC

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

SPIRV

[SPIR-V] Type inference must realize that a <1 x Type> vector type is not a legal vector type in LLT (#124560)

2025-02-13 17:46:42 +01:00

SystemZ

[SystemZ] Add codegen support for llvm.roundeven

2025-02-14 00:10:37 +01:00

Thumb

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

Thumb2

[ARM] Fix calling convention for __fp16 with big-endian (#126741)

2025-02-13 09:09:29 +00:00

VE

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

WebAssembly

[WebAssembly] Enable interleaved memory accesses (#125696)

2025-02-17 09:09:52 +00:00

WinCFGuard

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WinEH

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X86

[X86] combineConcatVectorOps - fold concat(EXTEND_VECTOR_INREG(x),EXTEND_VECTOR_INREG(y)) -> EXTEND_VECTOR_INREG(unpack(x,y)) (#127502)

2025-02-17 15:50:25 +00:00

XCore

[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#126811)

2025-02-12 09:19:00 +00:00

Xtensa

[CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamer

2024-12-22 21:11:32 -08:00