ad1a45b903
Currently, when SDAG is run on AArch64 and an `optnone` function is encountered, the selector is chosen as FastISel. AArch64 makes use of GlobalISel at O0 and this patch aims to align `optnone` with this functionality. A flag is exposed to enable this functionality for a given backend but, as AArch64 is currently the only backend I could find using GlobalISel at O0 this is the only one with it implemented. This flag is set when the target supports GlobalISel & GlobalISel hasn't been forced by the user, the target machine or by being at an optimisation level lower than `EnableGlobalISelAtO`. If this happens, the GlobalISel passes are included as shown in `llvm/test/CodeGen/AArch64/O3-pipeline.ll` and skipped by IRTranslator for functions not marked as `optnone`. In updating the tests based on this functionality, I found some unused check lines or run lines that mixed SDAG with GlobalISel pass names which have been fixed. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
55 lines
2.5 KiB
LLVM
55 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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@.str = private unnamed_addr constant [11 x i8] c"val = %ld\0A\00", align 1
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; Function Attrs: noinline optnone
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define dso_local void @set_large(i64 %val) #0 {
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entry:
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%val.addr = alloca i64, align 8
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%large = alloca [268435456 x i64], align 8
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%i = alloca i32, align 4
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store i64 %val, ptr %val.addr, align 8
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%0 = load i64, ptr %val.addr, align 8
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%arrayidx = getelementptr inbounds [268435456 x i64], ptr %large, i64 0, i64 %0
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store i64 1, ptr %arrayidx, align 8
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%1 = load i64, ptr %val.addr, align 8
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%arrayidx1 = getelementptr inbounds [268435456 x i64], ptr %large, i64 0, i64 %1
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%2 = load i64, ptr %arrayidx1, align 8
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%call = call i32 (ptr, ...) @printf(ptr @.str, i64 %2)
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ret void
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}
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declare dso_local i32 @printf(ptr, ...)
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attributes #0 = { noinline optnone "frame-pointer"="all" uwtable }
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; CHECK: stp x[[SPILL_REG1:[0-9]+]], x[[SPILL_REG2:[0-9]+]], [sp, #-[[SPILL_OFFSET1:[0-9]+]]]
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; CHECK-NEXT: .cfi_def_cfa_offset [[SPILL_OFFSET1]]
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; CHECK-NEXT: str x[[SPILL_REG3:[0-9]+]], [sp, #[[SPILL_OFFSET2:[0-9]+]]]
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; CHECK-NEXT: mov x[[FRAME:[0-9]+]], sp
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; CHECK-NEXT: .cfi_def_cfa w[[FRAME]], [[SPILL_OFFSET1]]
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; CHECK-COUNT-128: sub sp, sp, #[[STACK1:[0-9]+]], lsl #12
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; CHECK-NEXT: sub sp, sp, #[[STACK2:[0-9]+]], lsl #12
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; CHECK-NEXT: sub sp, sp, #[[STACK3:[0-9]+]]
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; CHECK: sub x[[INDEX:[0-9]+]], x[[FRAME]], #8
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; CHECK-NEXT: str x0, [x[[INDEX]]]
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; CHECK-NEXT: ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
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; CHECK-NEXT: add x10, sp, #8
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; CHECK-NEXT: mov x11, #1 // =0x1
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; CHECK-NEXT: str x11, [x10, x9, lsl #3]
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; CHECK-NEXT: ldr x8, [x8]
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; CHECK-NEXT: ldr x1, [x10, x8, lsl #3]
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; CHECK-NEXT: adrp x0, .L.str
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; CHECK-NEXT: add x0, x0, :lo12:.L.str
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; CHECK: bl printf
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; CHECK-COUNT-128: add sp, sp, #[[STACK1]], lsl #12
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; CHECK-NEXT: add sp, sp, #[[STACK2]], lsl #12
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; CHECK-NEXT: add sp, sp, #[[STACK3]]
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; CHECK-NEXT: .cfi_def_cfa wsp, [[SPILL_OFFSET1]]
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; CHECK-NEXT: ldr x[[SPILL_REG3]], [sp, #[[SPILL_OFFSET2]]]
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; CHECK-NEXT: ldp x[[SPILL_REG1]], x[[SPILL_REG2]], [sp], #[[SPILL_OFFSET1]]
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore w[[SPILL_REG3]]
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; CHECK-NEXT: .cfi_restore w[[SPILL_REG2]]
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; CHECK-NEXT: .cfi_restore w[[SPILL_REG1]]
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