d226f1b161
Regenerate checks after two recent commits that caused extra stuff to be added at the end of assembly lines, so the existing checks did not fail. - #179414 added "nv" to loads and stores on GFX1250. - #185774 added "msbs" comments on setreg instructions.
88 lines
4.2 KiB
LLVM
88 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=instcombine < %s | llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
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; RUN: opt -passes=instcombine < %s | llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
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; RUN: opt -passes=instcombine < %s | llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
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; RUN: opt -passes=instcombine < %s | llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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; The address calculation can be simplified and folded because of known bits of mbcnt.
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define amdgpu_ps <2 x float> @global_load_scale_add_foldable_knownbits(ptr addrspace(1) inreg %sbase) {
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; GFX12-LABEL: global_load_scale_add_foldable_knownbits:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: global_load_scale_add_foldable_knownbits:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 scale_offset
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: ; return to shader part epilog
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%v = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%mul = shl i32 %v, 1
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%add = add i32 %mul, 32
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%zext.offset = zext i32 %add to i64
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%gep = getelementptr inbounds float, ptr addrspace(1) %sbase, i64 %zext.offset
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%load = load <2 x float>, ptr addrspace(1) %gep
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ret <2 x float> %load
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}
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; The nsw/nuw helps the folding of address addition.
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define amdgpu_ps <2 x float> @global_load_scale_add_foldable_nowrap(ptr addrspace(1) inreg %sbase, i32 %v) {
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; GFX12-LABEL: global_load_scale_add_foldable_nowrap:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: global_load_scale_add_foldable_nowrap:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 scale_offset
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = shl nsw nuw i32 %v, 3
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%add = add nsw nuw i32 %mul, 128
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%zext.offset = zext i32 %add to i64
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%gep = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
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%load = load <2 x float>, ptr addrspace(1) %gep
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ret <2 x float> %load
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}
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; Address calculation cannot be folded because possible overflow during addition.
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define amdgpu_ps <2 x float> @global_load_scale_add_unfoldable(ptr addrspace(1) inreg %sbase, i32 %v) {
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; GFX12-LABEL: global_load_scale_add_unfoldable:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_lshl_add_u32 v0, v0, 3, 0x80
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; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: global_load_scale_add_unfoldable:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_lshl_add_u32 v0, v0, 3, 0x80
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; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[2:3]
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; GFX1250-NEXT: s_wait_loadcnt 0x0
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; GFX1250-NEXT: ; return to shader part epilog
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%mul = shl i32 %v, 3
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%add = add i32 %mul, 128
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%zext.offset = zext i32 %add to i64
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%gep = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
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%load = load <2 x float>, ptr addrspace(1) %gep
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ret <2 x float> %load
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX12-GISEL: {{.*}}
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; GFX12-SDAG: {{.*}}
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; GFX1250-GISEL: {{.*}}
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; GFX1250-SDAG: {{.*}}
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