llvm-project/llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
Janek van Oirschot 8da1bb891e
Reapply "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325) (#184114)
Reapplies commit 341cdbc9703d3cdd151f897b63548387f0017f49
2026-03-02 14:47:35 +00:00

21 lines
720 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
define amdgpu_kernel void @foo(ptr %0) {
; CHECK-LABEL: foo:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: v_mov_b32_e32 v4, 0
; CHECK-NEXT: v_mov_b32_e32 v6, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; CHECK-NEXT: flat_store_dwordx3 v[2:3], v[4:6]
; CHECK-NEXT: s_endpgm
entry:
%1 = getelementptr inbounds i8, ptr %0, i64 4
store i32 0, ptr %0, align 4
store i64 0, ptr %1, align 4
ret void
}