4ca2caeab6
Implements the HLSL ddx_fine and ddy_fine intrinsics. For the SPIRV backend the intrinsics are ensured to be unavailable in opencl (as they require fragment execution stage). Closes https://github.com/llvm/llvm-project/issues/99098 Closes https://github.com/llvm/llvm-project/issues/99101
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; RUN: not opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s 2>&1 | FileCheck --check-prefixes=CHECK-TYPE %s
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; RUN: not opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s 2>&1 | FileCheck --check-prefixes=CHECK-STAGE %s
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; DXIL operation ddx.fine does not support double overload type
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; CHECK-TYPE: in function ddx.fine
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; CHECK-TYPE-SAME: Cannot create DerivFineX operation: Invalid overload type
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; Function Attrs: noinline nounwind optnone
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define noundef double @ddx.fine_double(double noundef %a) #0 {
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entry:
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%a.addr = alloca double, align 8
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store double %a, ptr %a.addr, align 8
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%0 = load double, ptr %a.addr, align 8
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%dx.ddx.fine = call double @llvm.dx.ddx.fine.f64(double %0)
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ret double %dx.ddx.fine
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}
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; DXIL operation ddx.fine does not support compute shader stage
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; CHECK-STAGE: in function ddx.fine
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; CHECK-STAGE-SAME: Cannot create DerivFineX operation: Invalid stage
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; Function Attrs: noinline nounwind optnone
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define noundef float @ddx.fine_float(float noundef %a) #0 {
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entry:
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%a.addr = alloca float, align 8
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store float %a, ptr %a.addr, align 8
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%0 = load float, ptr %a.addr, align 8
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%dx.ddx.fine = call float @llvm.dx.ddx.fine.f32(float %0)
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ret float %dx.ddx.fine
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}
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