c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
127 lines
3.7 KiB
LLVM
127 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
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;
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; Test loading-and-store fp16 vectors.
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define void @fun0(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lgh %r0, 0(%r2)
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; CHECK-NEXT: lgh %r1, 2(%r2)
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; CHECK-NEXT: sllg %r0, %r0, 48
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; CHECK-NEXT: ldgr %f0, %r0
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; CHECK-NEXT: lgh %r0, 4(%r2)
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; CHECK-NEXT: sllg %r1, %r1, 48
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; CHECK-NEXT: ldgr %f1, %r1
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; CHECK-NEXT: lgh %r1, 6(%r2)
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; CHECK-NEXT: sllg %r0, %r0, 48
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; CHECK-NEXT: ldgr %f2, %r0
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; CHECK-NEXT: lgh %r0, 8(%r2)
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; CHECK-NEXT: sllg %r1, %r1, 48
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; CHECK-NEXT: ldgr %f3, %r1
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; CHECK-NEXT: lgh %r1, 10(%r2)
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; CHECK-NEXT: sllg %r0, %r0, 48
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; CHECK-NEXT: ldgr %f4, %r0
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; CHECK-NEXT: lgh %r0, 12(%r2)
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; CHECK-NEXT: sllg %r1, %r1, 48
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; CHECK-NEXT: lgh %r2, 14(%r2)
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; CHECK-NEXT: ldgr %f5, %r1
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; CHECK-NEXT: sllg %r0, %r0, 48
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; CHECK-NEXT: ldgr %f6, %r0
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; CHECK-NEXT: sllg %r0, %r2, 48
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; CHECK-NEXT: ldgr %f7, %r0
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; CHECK-NEXT: lgdr %r0, %f7
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 14(%r3)
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; CHECK-NEXT: lgdr %r0, %f6
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 12(%r3)
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; CHECK-NEXT: lgdr %r0, %f5
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 10(%r3)
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; CHECK-NEXT: lgdr %r0, %f4
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 8(%r3)
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; CHECK-NEXT: lgdr %r0, %f3
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 6(%r3)
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; CHECK-NEXT: lgdr %r0, %f2
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 4(%r3)
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; CHECK-NEXT: lgdr %r0, %f1
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 2(%r3)
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 0(%r3)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: fun0:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: vl %v0, 0(%r2), 3
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; VECTOR-NEXT: vst %v0, 0(%r3), 3
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; VECTOR-NEXT: br %r14
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%L = load <8 x half>, ptr %Src
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store <8 x half> %L, ptr %Dst
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ret void
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}
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define void @fun1(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lgh %r0, 4(%r2)
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; CHECK-NEXT: lgh %r1, 6(%r2)
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; CHECK-NEXT: l %r2, 0(%r2)
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; CHECK-NEXT: sllg %r0, %r0, 48
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; CHECK-NEXT: ldgr %f0, %r0
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; CHECK-NEXT: sllg %r0, %r1, 48
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; CHECK-NEXT: ldgr %f1, %r0
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; CHECK-NEXT: st %r2, 0(%r3)
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; CHECK-NEXT: lgdr %r0, %f1
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 6(%r3)
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 4(%r3)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: fun1:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: l %r0, 0(%r2)
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; VECTOR-NEXT: vlreph %v0, 4(%r2)
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; VECTOR-NEXT: vlreph %v1, 6(%r2)
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; VECTOR-NEXT: vsteh %v1, 6(%r3), 0
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; VECTOR-NEXT: vsteh %v0, 4(%r3), 0
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; VECTOR-NEXT: st %r0, 0(%r3)
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; VECTOR-NEXT: br %r14
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%L = load <4 x half>, ptr %Src
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store <4 x half> %L, ptr %Dst
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ret void
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}
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define void @fun2(ptr %Src, ptr %Dst) {
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; CHECK-LABEL: fun2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lg %r0, 24(%r2)
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; CHECK-NEXT: lg %r1, 16(%r2)
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; CHECK-NEXT: lg %r4, 8(%r2)
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; CHECK-NEXT: lg %r2, 0(%r2)
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; CHECK-NEXT: stg %r0, 24(%r3)
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; CHECK-NEXT: stg %r1, 16(%r3)
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; CHECK-NEXT: stg %r4, 8(%r3)
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; CHECK-NEXT: stg %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: fun2:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: vl %v0, 16(%r2), 4
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; VECTOR-NEXT: vl %v1, 0(%r2), 4
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; VECTOR-NEXT: vst %v1, 0(%r3), 4
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; VECTOR-NEXT: vst %v0, 16(%r3), 4
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; VECTOR-NEXT: br %r14
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%L = load <16 x half>, ptr %Src
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store <16 x half> %L, ptr %Dst
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ret void
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}
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