c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
67 lines
1.5 KiB
LLVM
67 lines
1.5 KiB
LLVM
; Test scalar_to_vector expansion.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8.
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define <16 x i8> @f1(i8 %val) {
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; CHECK-LABEL: f1:
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; CHECK: vlvgb %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <16 x i8> undef, i8 %val, i32 0
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ret <16 x i8> %ret
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}
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; Test v8i16.
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define <8 x i16> @f2(i16 %val) {
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; CHECK-LABEL: f2:
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; CHECK: vlvgh %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <8 x i16> undef, i16 %val, i32 0
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ret <8 x i16> %ret
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}
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; Test v4i32.
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define <4 x i32> @f3(i32 %val) {
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; CHECK-LABEL: f3:
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; CHECK: vlvgf %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <4 x i32> undef, i32 %val, i32 0
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ret <4 x i32> %ret
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}
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; Test v2i64. Here we load %val into both halves.
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define <2 x i64> @f4(i64 %val) {
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; CHECK-LABEL: f4:
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; CHECK: vlvgp %v24, %r2, %r2
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; CHECK: br %r14
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%ret = insertelement <2 x i64> undef, i64 %val, i32 0
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ret <2 x i64> %ret
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}
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; Test v8f16, which is just a move.
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define <8 x half> @f5(half %val) {
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; CHECK-LABEL: f5:
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; CHECK: vlr %v24, %v0
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; CHECK: br %r14
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%ret = insertelement <8 x half> undef, half %val, i32 0
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ret <8 x half> %ret
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}
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; Likewise v4f32,
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define <4 x float> @f6(float %val) {
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; CHECK-LABEL: f6:
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; CHECK: vlr %v24, %v0
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; CHECK: br %r14
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%ret = insertelement <4 x float> undef, float %val, i32 0
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ret <4 x float> %ret
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}
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; and v2f64.
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define <2 x double> @f7(double %val) {
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; CHECK-LABEL: f7:
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; CHECK: vlr %v24, %v0
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; CHECK: br %r14
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%ret = insertelement <2 x double> undef, double %val, i32 0
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ret <2 x double> %ret
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}
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