72c3c30452
The CWSR trap handler needs to save and restore the VGPRs. When dynamic VGPRs are in use, the fixed function hardware will only allocate enough space for one VGPR block. The rest will have to be stored in scratch, at offset 0. This patch allocates the necessary space by: - generating a prologue that checks at runtime if we're on a compute queue (since CWSR only works on compute queues); for this we will have to check the ME_ID bits of the ID_HW_ID2 register - if that is non-zero, we can assume we're on a compute queue and initialize the SP and FP with enough room for the dynamic VGPRs - forcing all compute entry functions to use a FP so they can access their locals/spills correctly (this isn't ideal but it's the quickest to implement) Note that at the moment we allocate enough space for the theoretical maximum number of VGPRs that can be allocated dynamically (for blocks of 16 registers, this will be 128, of which we subtract the first 16, which are already allocated by the fixed function hardware). Future patches may decide to allocate less if they can prove the shader never allocates that many blocks. Also note that this should not affect any reported stack sizes (e.g. PAL backend_stack_size etc).
126 lines
6.5 KiB
LLVM
126 lines
6.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
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; Test that debug instructions do not change long branch reserved serialized through
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; MIR.
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; CHECK-LABEL: {{^}}name: uniform_long_forward_branch_debug
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: explicitKernArgSize: 12
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; CHECK-NEXT: maxKernArgAlign: 8
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; CHECK-NEXT: ldsSize: 0
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; CHECK-NEXT: gdsSize: 0
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; CHECK-NEXT: dynLDSAlign: 1
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; CHECK-NEXT: isEntryFunction: true
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; CHECK-NEXT: isChainFunction: false
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; CHECK-NEXT: noSignedZerosFPMath: false
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; CHECK-NEXT: memoryBound: false
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; CHECK-NEXT: waveLimiter: false
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; CHECK-NEXT: hasSpilledSGPRs: false
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; CHECK-NEXT: hasSpilledVGPRs: false
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; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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; CHECK-NEXT: frameOffsetReg: '$fp_reg'
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; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
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; CHECK-NEXT: bytesInStackArgArea: 0
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; CHECK-NEXT: returnsVoid: true
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; CHECK-NEXT: argumentInfo:
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; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
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; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
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; CHECK-NEXT: psInputAddr: 0
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; CHECK-NEXT: psInputEnable: 0
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; CHECK-NEXT: maxMemoryClusterDWords: 8
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; CHECK-NEXT: mode:
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; CHECK-NEXT: ieee: true
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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; CHECK-NEXT: BitsOf32BitAddress: 0
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; CHECK-NEXT: occupancy: 10
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; CHECK-NEXT: vgprForAGPRCopy: ''
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; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
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; CHECK-NEXT: longBranchReservedReg: '$sgpr2_sgpr3'
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; CHECK-NEXT: hasInitWholeWave: false
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; CHECK-NEXT: scratchReservedForDynamicVGPRs: 0
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; CHECK-NEXT: body:
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define amdgpu_kernel void @uniform_long_forward_branch_debug(ptr addrspace(1) %arg, i32 %arg1) #0 !dbg !5 {
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bb0:
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%uniform_long_forward_branch_debug.kernarg.segment = call nonnull align 16 dereferenceable(12) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr(), !dbg !11
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%arg1.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %uniform_long_forward_branch_debug.kernarg.segment, i64 8, !dbg !11, !amdgpu.uniform !7
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%arg1.load = load i32, ptr addrspace(4) %arg1.kernarg.offset, align 8, !dbg !11, !invariant.load !7
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%tmp = icmp eq i32 %arg1.load, 0, !dbg !11
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call void @llvm.dbg.value(metadata i1 %tmp, metadata !9, metadata !DIExpression()), !dbg !11
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br i1 %tmp, label %bb3, label %Flow, !dbg !12, !amdgpu.uniform !7
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Flow: ; preds = %bb3, %bb0
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%0 = phi i1 [ false, %bb3 ], [ true, %bb0 ], !dbg !12
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br i1 %0, label %bb2, label %bb4, !dbg !12, !amdgpu.uniform !7
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bb2: ; preds = %Flow
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store volatile i32 17, ptr addrspace(1) poison, align 4, !dbg !13
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br label %bb4, !dbg !14, !amdgpu.uniform !7
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bb3: ; preds = %bb0
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call void asm sideeffect "v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", ""(), !dbg !15
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br label %Flow, !dbg !16, !amdgpu.uniform !7
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bb4: ; preds = %bb2, %Flow
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%arg.kernarg.offset1 = bitcast ptr addrspace(4) %uniform_long_forward_branch_debug.kernarg.segment to ptr addrspace(4), !dbg !11, !amdgpu.uniform !7
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%arg.load = load ptr addrspace(1), ptr addrspace(4) %arg.kernarg.offset1, align 16, !dbg !11, !invariant.load !7
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store volatile i32 63, ptr addrspace(1) %arg.load, align 4, !dbg !17
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ret void, !dbg !18
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare void @llvm.dbg.value(metadata, metadata, metadata) #1
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare { i1, i64 } @llvm.amdgcn.if.i64(i1) #2
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare { i1, i64 } @llvm.amdgcn.else.i64.i64(i64) #2
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; Function Attrs: convergent nocallback nofree nounwind willreturn memory(none)
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declare i64 @llvm.amdgcn.if.break.i64(i1, i64) #3
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare i1 @llvm.amdgcn.loop.i64(i64) #2
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare void @llvm.amdgcn.end.cf.i64(i64) #2
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attributes #0 = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #2 = { convergent nocallback nofree nounwind willreturn }
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attributes #3 = { convergent nocallback nofree nounwind willreturn memory(none) }
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!llvm.dbg.cu = !{!0}
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!llvm.debugify = !{!2, !3}
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!llvm.module.flags = !{!4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
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!1 = !DIFile(filename: "temp.ll", directory: "/")
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!2 = !{i32 8}
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!3 = !{i32 1}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "uniform_long_forward_branch_debug", linkageName: "uniform_long_forward_branch_debug", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
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!6 = !DISubroutineType(types: !7)
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!7 = !{}
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!8 = !{!9}
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!9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10)
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!10 = !DIBasicType(name: "ty8", size: 8, encoding: DW_ATE_unsigned)
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!11 = !DILocation(line: 1, column: 1, scope: !5)
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!12 = !DILocation(line: 2, column: 1, scope: !5)
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!13 = !DILocation(line: 3, column: 1, scope: !5)
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!14 = !DILocation(line: 4, column: 1, scope: !5)
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!15 = !DILocation(line: 5, column: 1, scope: !5)
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!16 = !DILocation(line: 6, column: 1, scope: !5)
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!17 = !DILocation(line: 7, column: 1, scope: !5)
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!18 = !DILocation(line: 8, column: 1, scope: !5)
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