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llvm-project/llvm/lib/Target/Mips
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Sander de Smalen 62bbe3fffc
Fix buildbot failure by explicitly disabling partial reductions in TTI. (#190165) 
Partial reductions were previously disabled by default, but by
implementing a generic cost-model in BasicTTIImpl (#189905) this now
accidentally enables the use of those when vectorising loops for targets
that may not support this yet.
2026-04-03 16:33:39 +01:00
..
AsmParser
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
Disassembler
MIPSr6: Set FSELECT Legal for f64 (#173591)
2025-12-26 18:49:41 +08:00
MCTargetDesc
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
TargetInfo
…
CMakeLists.txt
MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)
2026-03-12 07:55:16 +08:00
MicroMips32r6InstrFormats.td
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MicroMips32r6InstrInfo.td
MIPSr6: Set FSELECT Legal for f64 (#173591)
2025-12-26 18:49:41 +08:00
MicroMipsDSPInstrFormats.td
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MicroMipsDSPInstrInfo.td
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MicroMipsInstrFormats.td
…
MicroMipsInstrFPU.td
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MicroMipsInstrInfo.td
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MicroMipsSizeReduction.cpp
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Mips16FrameLowering.cpp
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Mips16FrameLowering.h
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Mips16HardFloat.cpp
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Mips16HardFloatInfo.cpp
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Mips16HardFloatInfo.h
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Mips16InstrFormats.td
…
Mips16InstrInfo.cpp
[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
2026-01-23 00:19:03 -08:00
Mips16InstrInfo.h
CodeGen: Remove TRI arguments from stack load/store hooks (#158240)
2025-11-10 16:24:39 -08:00
Mips16InstrInfo.td
…
Mips16ISelDAGToDAG.cpp
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Mips16ISelDAGToDAG.h
…
Mips16ISelLowering.cpp
CodeGen: Move libcall lowering configuration to subtarget (#168621)
2025-11-25 11:59:56 -05:00
Mips16ISelLowering.h
CodeGen: Move libcall lowering configuration to subtarget (#168621)
2025-11-25 11:59:56 -05:00
Mips16RegisterInfo.cpp
…
Mips16RegisterInfo.h
…
Mips32r6InstrFormats.td
…
Mips32r6InstrInfo.td
MIPSr6: Set FSELECT Legal for f64 (#173591)
2025-12-26 18:49:41 +08:00
Mips64InstrInfo.td
[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)
2026-01-28 04:32:59 -05:00
Mips64r6InstrInfo.td
[CodeGen] Remove unused first operand of SUBREG_TO_REG (#179690)
2026-02-04 17:35:21 +00:00
Mips.h
MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)
2026-03-12 07:55:16 +08:00
Mips.td
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MipsAnalyzeImmediate.cpp
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MipsAnalyzeImmediate.h
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MipsAsmPrinter.cpp
[MC] Rename PrivateGlobalPrefix to InternalSymbolPrefix. NFC (#185164)
2026-03-10 01:03:27 -07:00
MipsAsmPrinter.h
[X86][WinEH] Insert nop after unwinding inline assembly (#176393)
2026-01-19 09:09:04 +01:00
MipsBranchExpansion.cpp
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MipsCallingConv.td
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MipsCallLowering.cpp
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
2026-03-03 10:11:25 +08:00
MipsCallLowering.h
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MipsCCState.cpp
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MipsCCState.h
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MipsCombine.td
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MipsCondMov.td
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MipsConstantIslandPass.cpp
[Mips] Use getSigned() for LwConstant32 immedate
2025-12-16 09:28:33 +01:00
MipsDelaySlotFiller.cpp
[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)
2026-01-28 04:32:59 -05:00
MipsDSPInstrFormats.td
…
MipsDSPInstrInfo.td
[Mips] TableGen-erate SDNode descriptions (#168307)
2025-12-05 14:53:14 +00:00
MipsEVAInstrFormats.td
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MipsEVAInstrInfo.td
…
MipsExpandPseudo.cpp
MIPS/expandAtomicBinOp: Remove tailing kill dead register operands (#186055)
2026-03-13 08:29:35 +08:00
MipsFastISel.cpp
[CodeGen] Drop uses of BranchInst (#186391)
2026-03-13 21:51:38 +00:00
MipsFrameLowering.cpp
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MipsFrameLowering.h
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MipsInstrCompiler.td
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MipsInstrFormats.td
…
MipsInstrFPU.td
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MipsInstrInfo.cpp
[Mips] Correctly report sizes for PATCHABLE_* (#188229)
2026-04-01 14:35:07 +02:00
MipsInstrInfo.h
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)
2026-01-13 08:21:58 +05:30
MipsInstrInfo.td
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MipsInstructionSelector.cpp
[NFC][LLVM] Make MachineInstrBuilder::constrainAllUses return void (#179632)
2026-02-04 12:06:10 +01:00
MipsISelDAGToDAG.cpp
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MipsISelDAGToDAG.h
…
MipsISelLowering.cpp
[Mips] Remove NoNaNsFPMath uses (#183045)
2026-02-26 18:49:16 +08:00
MipsISelLowering.h
FastISel: Thread LibcallLoweringInfo through (#176799)
2026-01-19 20:44:48 +00:00
MipsLegalizerInfo.cpp
[NFC][LLVM] Make MachineInstrBuilder::constrainAllUses return void (#179632)
2026-02-04 12:06:10 +01:00
MipsLegalizerInfo.h
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MipsMachineFunction.cpp
…
MipsMachineFunction.h
…
MipsMCInstLower.cpp
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MipsMCInstLower.h
…
MipsModuleISelDAGToDAG.cpp
…
MipsMSAInstrFormats.td
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MipsMSAInstrInfo.td
[Mips] TableGen-erate SDNode descriptions (#168307)
2025-12-05 14:53:14 +00:00
MipsMTInstrFormats.td
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MipsMTInstrInfo.td
MIPSr6: Set FSELECT Legal for f64 (#173591)
2025-12-26 18:49:41 +08:00
MipsMulMulBugPass.cpp
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MipsOptimizePICCall.cpp
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MipsOptionRecord.h
[Mips] Remove implicit conversions of MCRegister to unsigned. NFC (#167645)
2025-11-12 08:43:55 -08:00
MipsOs16.cpp
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MipsPfmCounters.td
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MipsPostLegalizerCombiner.cpp
[NFC] Removes unused Combiner dependency on TargetPassConfig (#188365)
2026-03-30 08:58:22 -07:00
MipsPreLegalizerCombiner.cpp
[NFC] Removes unused Combiner dependency on TargetPassConfig (#188365)
2026-03-30 08:58:22 -07:00
MipsRegisterBankInfo.cpp
[Mips] Add support for Mips::GPR64Idx in MipsRegisterBankInfo (#173534)
2025-12-26 18:49:55 +08:00
MipsRegisterBankInfo.h
[Mips] Add support for Mips::GPR64Idx in MipsRegisterBankInfo (#173534)
2025-12-26 18:49:55 +08:00
MipsRegisterBanks.td
[Mips] Add support for Mips::GPR64Idx in MipsRegisterBankInfo (#173534)
2025-12-26 18:49:55 +08:00
MipsRegisterInfo.cpp
[mips][micromips] Add mayRaiseFPException to appropriate instructions, mark all instructions that read FCSR (FCR31) rounding bits as doing so (#170322)
2025-12-18 23:06:36 +01:00
MipsRegisterInfo.h
…
MipsRegisterInfo.td
MIPSr6: Set FSELECT Legal for f64 (#173591)
2025-12-26 18:49:41 +08:00
MipsSchedule.td
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MipsScheduleGeneric.td
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MipsScheduleI6400.td
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MipsScheduleP5600.td
…
MipsSEFrameLowering.cpp
[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
2026-01-23 00:19:03 -08:00
MipsSEFrameLowering.h
…
MipsSEInstrInfo.cpp
MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)
2026-03-12 07:55:16 +08:00
MipsSEInstrInfo.h
CodeGen: Remove TRI arguments from stack load/store hooks (#158240)
2025-11-10 16:24:39 -08:00
MipsSEISelDAGToDAG.cpp
[CodeGen] Remove unused first operand of SUBREG_TO_REG (#179690)
2026-02-04 17:35:21 +00:00
MipsSEISelDAGToDAG.h
…
MipsSEISelLowering.cpp
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MipsSEISelLowering.h
[Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (#178942)
2026-03-22 23:48:00 -04:00
MipsSelectionDAGInfo.cpp
[Mips] TableGen-erate SDNode descriptions (#168307)
2025-12-05 14:53:14 +00:00
MipsSelectionDAGInfo.h
[Mips] TableGen-erate SDNode descriptions (#168307)
2025-12-05 14:53:14 +00:00
MipsSERegisterInfo.cpp
…
MipsSERegisterInfo.h
…
MipsSetMachineRegisterFlags.cpp
MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)
2026-03-12 07:55:16 +08:00
MipsSubtarget.cpp
[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)
2026-01-28 04:32:59 -05:00
MipsSubtarget.h
[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)
2026-01-28 04:32:59 -05:00
MipsTargetMachine.cpp
MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820)
2026-03-12 07:55:16 +08:00
MipsTargetMachine.h
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MipsTargetObjectFile.cpp
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
MipsTargetObjectFile.h
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
MipsTargetTransformInfo.cpp
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MipsTargetTransformInfo.h
Fix buildbot failure by explicitly disabling partial reductions in TTI. (#190165)
2026-04-03 16:33:39 +01:00
MSA.txt
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Relocation.txt
…