92c80529dd
Consider large operands in G_MERGE_VALUES and G_UNMERGE_VALUES as
Ambiguous during regbank selection.
Introducing new InstType AmbiguousWithMergeOrUnmerge which will
allow us to recognize whether to narrow scalar or use s64:fprb.
This change exposed a bug when reusing data from TypeInfoForMF.
Thus when Instr is about to get destroyed (using narrow scalar)
clear its data in TypeInfoForMF. Internal data is saved based on
Instr's address, and it will no longer be valid.
Add detailed asserts for InstType and operand size.
Generate generic instructions instead of MIPS target instructions
during argument lowering and custom legalizer.
Select G_UNMERGE_VALUES and G_MERGE_VALUES when proper banks are
selected: {s32:gprb, s32:gprb, s64:fprb} for G_UNMERGE_VALUES and
{s64:fprb, s32:gprb, s32:gprb} for G_MERGE_VALUES.
Update tests. One improvement is when floating point argument in
gpr(or two gprs) gets passed to another function through gpr
unnecessary fpr-to-gpr moves are no longer generated.
Differential Revision: https://reviews.llvm.org/D74623
365 lines
13 KiB
YAML
365 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
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--- |
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define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i32 [ %a, %cond.true ], [ %b, %cond.false ]
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ret i32 %cond
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}
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define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
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ret i64 %cond
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}
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define float @phi_float(i1 %cnd, float %a, float %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
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ret float %cond
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}
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define double @phi_double(double %a, double %b, i1 %cnd) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
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ret double %cond
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}
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...
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---
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name: phi_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32FP32-LABEL: name: phi_i32
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a1, $a2
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP32: $v0 = COPY [[PHI]]
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; MIPS32FP32: RetRA implicit $v0
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; MIPS32FP64-LABEL: name: phi_i32
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a1, $a2
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: bb.3.cond.end:
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; MIPS32FP64: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP64: $v0 = COPY [[PHI]]
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; MIPS32FP64: RetRA implicit $v0
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bb.1.entry:
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liveins: $a0, $a1, $a2
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%3:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = COPY $a2
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%6:gprb(s32) = G_CONSTANT i32 1
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%7:gprb(s32) = COPY %3(s32)
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%5:gprb(s32) = G_AND %7, %6
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G_BRCOND %5(s32), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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G_BR %bb.4
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bb.3.cond.false:
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bb.4.cond.end:
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%4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
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$v0 = COPY %4(s32)
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RetRA implicit $v0
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...
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---
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name: phi_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
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- { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
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body: |
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; MIPS32FP32-LABEL: name: phi_i64
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a2, $a3
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32FP32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
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; MIPS32FP32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
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; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
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; MIPS32FP32: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
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; MIPS32FP32: $v0 = COPY [[PHI]]
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; MIPS32FP32: $v1 = COPY [[PHI1]]
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; MIPS32FP32: RetRA implicit $v0, implicit $v1
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; MIPS32FP64-LABEL: name: phi_i64
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a2, $a3
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32FP64: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
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; MIPS32FP64: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
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; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: bb.3.cond.end:
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; MIPS32FP64: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
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; MIPS32FP64: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
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; MIPS32FP64: $v0 = COPY [[PHI]]
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; MIPS32FP64: $v1 = COPY [[PHI1]]
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; MIPS32FP64: RetRA implicit $v0, implicit $v1
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bb.1.entry:
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liveins: $a0, $a2, $a3
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%3:gprb(s32) = COPY $a0
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%4:gprb(s32) = COPY $a2
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%5:gprb(s32) = COPY $a3
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%8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
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%6:gprb(s32) = G_LOAD %8(p0) :: (load 4 from %fixed-stack.1, align 8)
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%9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
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%7:gprb(s32) = G_LOAD %9(p0) :: (load 4 from %fixed-stack.0)
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%14:gprb(s32) = G_CONSTANT i32 1
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%15:gprb(s32) = COPY %3(s32)
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%13:gprb(s32) = G_AND %15, %14
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G_BRCOND %13(s32), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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G_BR %bb.4
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bb.3.cond.false:
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bb.4.cond.end:
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%20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3
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%21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3
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$v0 = COPY %20(s32)
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$v1 = COPY %21(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: phi_float
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32FP32-LABEL: name: phi_float
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a1, $a2
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP32: $f0 = COPY [[PHI]]
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; MIPS32FP32: RetRA implicit $f0
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; MIPS32FP64-LABEL: name: phi_float
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a1, $a2
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
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; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: bb.3.cond.end:
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; MIPS32FP64: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP64: $f0 = COPY [[PHI]]
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; MIPS32FP64: RetRA implicit $f0
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bb.1.entry:
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liveins: $a0, $a1, $a2
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%3:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = COPY $a2
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%6:gprb(s32) = G_CONSTANT i32 1
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%7:gprb(s32) = COPY %3(s32)
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%5:gprb(s32) = G_AND %7, %6
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G_BRCOND %5(s32), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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G_BR %bb.4
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bb.3.cond.false:
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bb.4.cond.end:
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%4:gprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
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$f0 = COPY %4(s32)
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RetRA implicit $f0
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...
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---
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name: phi_double
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
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body: |
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; MIPS32FP32-LABEL: name: phi_double
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $d6, $d7
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; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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|
; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
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|
; MIPS32FP32: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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|
; MIPS32FP32: bb.2.cond.false:
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|
; MIPS32FP32: successors: %bb.3(0x80000000)
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|
; MIPS32FP32: bb.3.cond.end:
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|
; MIPS32FP32: [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
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|
; MIPS32FP32: $d0 = COPY [[PHI]]
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|
; MIPS32FP32: RetRA implicit $d0
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|
; MIPS32FP64-LABEL: name: phi_double
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|
; MIPS32FP64: bb.0.entry:
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|
; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $d6, $d7
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; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
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; MIPS32FP64: BNE [[ANDi]], $zero, %bb.1, implicit-def $at
|
|
; MIPS32FP64: J %bb.2, implicit-def $at
|
|
; MIPS32FP64: bb.1.cond.true:
|
|
; MIPS32FP64: successors: %bb.3(0x80000000)
|
|
; MIPS32FP64: J %bb.3, implicit-def $at
|
|
; MIPS32FP64: bb.2.cond.false:
|
|
; MIPS32FP64: successors: %bb.3(0x80000000)
|
|
; MIPS32FP64: bb.3.cond.end:
|
|
; MIPS32FP64: [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
|
|
; MIPS32FP64: $d0 = COPY [[PHI]]
|
|
; MIPS32FP64: RetRA implicit $d0
|
|
bb.1.entry:
|
|
liveins: $d6, $d7
|
|
|
|
%0:fprb(s64) = COPY $d6
|
|
%1:fprb(s64) = COPY $d7
|
|
%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
|
|
%3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
|
|
%7:gprb(s32) = G_CONSTANT i32 1
|
|
%8:gprb(s32) = COPY %3(s32)
|
|
%6:gprb(s32) = G_AND %8, %7
|
|
G_BRCOND %6(s32), %bb.2
|
|
G_BR %bb.3
|
|
|
|
bb.2.cond.true:
|
|
G_BR %bb.4
|
|
|
|
bb.3.cond.false:
|
|
|
|
bb.4.cond.end:
|
|
%5:fprb(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3
|
|
$d0 = COPY %5(s64)
|
|
RetRA implicit $d0
|
|
|
|
...
|