Guillaume Chatelet 48904e9452 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

82 lines
2.4 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
define void @ret_ptr(i8* %p) {entry: ret void}
...
---
name: ptr_arg_in_regs
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: ptr_arg_in_regs
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.p)
; MIPS32: $v0 = COPY [[LW]]
; MIPS32: RetRA implicit $v0
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: ptr_arg_on_stack
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
fixedStack:
- { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true }
body: |
bb.1.entry:
liveins: $a0, $a1, $a2, $a3
; MIPS32-LABEL: name: ptr_arg_on_stack
; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load 4 from %ir.p)
; MIPS32: $v0 = COPY [[LW1]]
; MIPS32: RetRA implicit $v0
%0:gprb(s32) = COPY $a0
%1:gprb(s32) = COPY $a1
%2:gprb(s32) = COPY $a2
%3:gprb(s32) = COPY $a3
%5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
%4:gprb(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 8)
%6:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
$v0 = COPY %6(s32)
RetRA implicit $v0
...
---
name: ret_ptr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: ret_ptr
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: $v0 = COPY [[COPY]]
; MIPS32: RetRA implicit $v0
%0:gprb(p0) = COPY $a0
$v0 = COPY %0(p0)
RetRA implicit $v0
...