Lei Huang a13ec9cd54

[PowerPC] Update data layout aligment of i128 to 16 (#118004) ...

Fix 64-bit PowerPC part of
https://github.com/llvm/llvm-project/issues/102783.

2024-12-09 18:02:24 -05:00

..

AArch64

[AArch64] Implement intrinsics for SME FP8 FMOPA (#118115)

2024-12-09 11:13:08 +00:00

AMDGPU

[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)

2024-12-09 11:52:05 -05:00

ARC

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ARM

Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)

2024-12-07 10:14:36 +03:00

AVR

[AVR] Simplify eocoding of load/store instructions (#118279)

2024-12-05 13:05:25 +08:00

BPF

Add the initializes attribute inference (#117104)

2024-11-20 19:15:23 -08:00

CSKY

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DirectX

[DirectX] Clean up extra vectors when lowering to buffer store (#116721)

2024-12-02 13:34:06 -08:00

Generic

[NFC][SelectionDAG] Replace generic @llvm.expect.with.probability codegen test with X86 test (#117848)

2024-12-01 17:46:08 -05:00

Hexagon

[Hexagon][NFC] Switch regalloc-bad-undef.mir to use generated CHECKs

2024-12-09 20:11:15 +08:00

Inputs

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Lanai

[CodeGen][NewPM] Port PeepholeOptimizer to NPM (#116326)

2024-11-18 11:02:01 +05:30

LoongArch

[LoongArch] Pre-commit tests for vector type llvm.bitreverse. NFC (#118053)

2024-12-09 19:43:12 +08:00

M68k

[M68k] Handle 16 bit MOVs to and from CCR (#114714)

2024-11-27 09:37:57 -08:00

Mips

[MachineLICM] Don't allow hoisting invariant loads across mem barrier. (#116987)

2024-11-21 10:25:04 +00:00

MIR

[RISCV][MIR] Move skip-mir-comment-trailing-whitespace.mir into RISCV subdirectory

2024-11-11 12:02:29 -08:00

MLRegAlloc

[MLGO] Remove extranous check lines from test input

2024-11-18 03:52:13 +00:00

MSP430

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NVPTX

Reland "[NVPTX] Add folding for cvt.rn.bf16x2.f32" (#116417)

2024-12-06 13:30:09 -08:00

PowerPC

[PowerPC] Update data layout aligment of i128 to 16 (#118004)

2024-12-09 18:02:24 -05:00

RISCV

[RISCV][GISel] Fallback in LowerCall for byval arguments. (#119251)

2024-12-09 14:22:05 -08:00

SPARC

[SPARC] Allow overaligned allocas (#107223)

2024-11-03 22:53:03 +07:00

SPIRV

[SPIR-V] Improve general validity of emitted code between passes (#119202)

2024-12-09 21:10:09 +01:00

SystemZ

Revert "[SystemZ] Add support for __builtin_setjmp and __builtin_longjmp (#116642)"

2024-12-07 00:55:54 +01:00

Thumb

Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)

2024-12-07 10:14:36 +03:00

Thumb2

Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)

2024-12-07 10:14:36 +03:00

VE

[SjLjEHPrepare] Configure call sites correctly (#117656)

2024-11-27 08:03:47 +03:00

WebAssembly

[WebAssembly] Support the new "Lime1" CPU (#112035)

2024-12-03 16:35:23 -08:00

WinCFGuard

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WinEH

[WinEH] Emit state stores for SEH scopes (#116546)

2024-11-27 15:43:20 -08:00

X86

[X86] Only fold to v16i32 VPDPWSSD on targets with useAVX512Regs enabled.

2024-12-09 11:56:29 +00:00

XCore

[RuntimeLibCalls] Consistently disable unavailable libcalls (#116214)

2024-11-15 15:46:28 +01:00

Xtensa

[UTC] Add support for Xtensa (#117441)

2024-11-23 20:43:05 +03:00