Simon Pilgrim dfbefe4a65

[CostModel][X86] Add missing AVX1 costs for PMULUDQ v4i64 pattern (#157475) ...

We need to account for AVX1 targets splitting 256-bit PMULUDQ style
patterns - we included a AVX2 cost, but missed out AVX1 despite v4i64
being a legal type

Noticed while working on #156568

2025-09-08 15:06:33 +00:00

..

AArch64

[AArch64] Give a higher cost for more expensive SVE FCMP instructions (#153816)

2025-09-04 19:50:39 +01:00

AMDGPU

[CostModel] Handle all cost kinds in getCmpSelInstrCost (#148233)

2025-07-15 18:08:52 +01:00

ARM

[ARM] Update a number of MVE tests to use -cost-kind=all. NFC

2025-08-26 20:43:27 +01:00

NVPTX

[NVPTX] Improve modeling of inline PTX (#130675)

2025-03-25 13:46:16 -07:00

PowerPC

[PowerPC] Update data layout aligment of i128 to 16 (#118004)

2024-12-09 18:02:24 -05:00

RISCV

[RISCV] Cost casts with illegal types that can't be legalized (#153030)

2025-08-12 00:29:39 +08:00

SystemZ

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

X86

[CostModel][X86] Add missing AVX1 costs for PMULUDQ v4i64 pattern (#157475)

2025-09-08 15:06:33 +00:00

free-intrinsics-datalayout.ll

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

free-intrinsics-no_info.ll

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

no_info.ll

…