Christudasan Devadasan a2dc4e02e7

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016) ...

This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.

2025-11-21 19:42:17 +05:30

..

AArch64

[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes are in use. (#168387)

2025-11-20 12:01:04 +00:00

AMDGPU

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)

2025-11-21 19:42:17 +05:30

ARC

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ARM

[DAG] Add strictfp implicit def reg after metadata. (#168282)

2025-11-17 10:57:21 +00:00

AVR

[AVR] Fix occasional corruption in stack passed params

2025-10-24 08:45:10 +08:00

BPF

[BPF] add allows-misaligned-mem-access target feature (#167013)

2025-11-13 08:50:52 -08:00

CSKY

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DirectX

[HLSL] Implement the fwidth intrinsic for DXIL and SPIR-V target (#161378)

2025-11-20 07:38:32 -05:00

Generic

[IR] llvm.reloc.none intrinsic for no-op symbol references (#147427)

2025-11-06 08:52:46 -08:00

Hexagon

[Hexagon] Enable soft bf16 in hexagon (#167924)

2025-11-19 09:52:46 -06:00

Inputs

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Lanai

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LoongArch

Reland "[LoongArch] Add isSafeToMove hook to prevent unsafe instruction motion" (#167465)

2025-11-12 08:51:08 +08:00

M68k

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Mips

[GlobalISel] Combine away G_UNMERGE(G_IMPLICITDEF). (#119183)

2025-10-28 09:57:31 +00:00

MIR

[GlobalISel] Make scalar G_SHUFFLE_VECTOR illegal. (#140508)

2025-10-24 08:21:35 +01:00

MIR2Vec

[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)

2025-11-19 15:44:02 +00:00

MLRegAlloc

[MLGO] Remove Extra Dev Mode Features (#167273)

2025-11-10 08:40:28 -08:00

MSP430

MSP430: Remove more default compiler-rt calls (#164752)

2025-10-23 15:23:02 +09:00

NVPTX

[NVPTX] Support for dense and sparse MMA intrinsics with block scaling. (#163561)

2025-11-21 17:43:52 +05:30

PowerPC

[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)

2025-11-21 12:26:58 +05:30

RISCV

[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)

2025-11-21 05:04:05 +00:00

SPARC

[Sparc] Optimize compare instruction (#167140)

2025-11-14 23:11:38 +07:00

SPIRV

[HLSL] Implement the fwidth intrinsic for DXIL and SPIR-V target (#161378)

2025-11-20 07:38:32 -05:00

SystemZ

CodeGen: Remove target hook for terminal rule (#165962)

2025-11-12 21:12:19 +00:00

Thumb

[test][ARM] Remove unsafe-fp-math-uses (NFC) (#164744)

2025-10-23 15:07:46 +08:00

Thumb2

DAG: Use poison when widening build_vector (#167631)

2025-11-12 20:17:41 +00:00

VE

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WebAssembly

[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG (#167529)

2025-11-20 08:57:08 +00:00

WinCFGuard

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WinEH

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X86

[X86] Lower mathlib call ldexp into scalef when avx512 is enabled (#166839)

2025-11-20 16:39:45 +00:00

XCore

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Xtensa

[Xtensa] Fix S32C1I instruction encoding and copyPhysReg. (#165174)

2025-11-05 20:27:11 +03:00