Adhemerval Zanella a3cefa5d64 [AArch64] Optimize floating point materialization
This patch follows some ideas from r352866 to optimize the floating
point materialization even further. It changes isFPImmLegal to
considere up to 2 mov instruction or up to 5 in case subtarget has
fused literals.

The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but
the mov+fmov sequence is always better because of the reduced d-cache
pressure. The timings are still the same if you consider movw+movk+fmov
vs. adrp+ldr will be fused (although one instruction longer).

Reviewers: efriedma

Differential Revision: https://reviews.llvm.org/D58460

llvm-svn: 356390
2019-03-18 18:45:57 +00:00
..
2017-06-01 14:24:31 +00:00
2016-10-26 18:49:16 +00:00
2018-08-02 01:54:12 +00:00
2016-10-18 20:41:30 +00:00
2018-02-26 23:19:25 +00:00
2017-05-23 06:08:37 +00:00
2016-05-26 12:42:55 +00:00
2018-07-11 10:39:50 +00:00
2018-02-26 23:19:25 +00:00
2018-02-16 20:00:57 +00:00