e6bf48d110
As of rev ea222be0d, LLVMs assembler will actually try to honour the "fill value" part of p2align directives. X86 printed these as 0x90, which isn't actually what it wanted: we want multi-byte nops for .text padding. Compiling via a textual assembly file produces single-byte nop padding since ea222be0d but the built-in assembler will produce multi-byte nops. This divergent behaviour is undesirable. To fix: don't set the byte padding field for x86, which allows the assembler to pick multi-byte nops. Test that we get the same multi-byte padding when compiled via textual assembly or directly to object file. Added same-align-bytes-with-llasm-llobj.ll to that effect, updated numerous other tests to not contain check-lines for the explicit padding.
92 lines
2.3 KiB
LLVM
92 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64 -mattr=+zu | FileCheck %s
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define i16 @i8(i8 %x) nounwind {
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; CHECK-LABEL: i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpb $3, %dil
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; CHECK-NEXT: setzuae %al
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%t0 = icmp ugt i8 %x, 2
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%zext = zext i1 %t0 to i16
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ret i16 %zext
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}
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define i16 @i16(i16 %x) nounwind {
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; CHECK-LABEL: i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpw $2, %di
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; CHECK-NEXT: setzub %al
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%t0 = icmp ult i16 %x, 2
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%if = select i1 %t0, i16 1, i16 0
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ret i16 %if
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}
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define i32 @i32(i32 %x) nounwind {
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; CHECK-LABEL: i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: setzue %al
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; CHECK-NEXT: retq
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%t0 = icmp eq i32 %x, 1
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%if = select i1 %t0, i32 1, i32 0
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ret i32 %if
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}
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define i64 @i64(i64 %x) nounwind {
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; CHECK-LABEL: i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpq $1, %rdi
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; CHECK-NEXT: setzune %al
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; CHECK-NEXT: retq
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%t0 = icmp ne i64 %x, 1
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%if = select i1 %t0, i64 1, i64 0
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ret i64 %if
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}
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define i32 @flags_copy_lowering() nounwind {
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; CHECK-LABEL: flags_copy_lowering:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB4_1: # %bb1
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: addl %edx, 0
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; CHECK-NEXT: setb %sil
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; CHECK-NEXT: adcl $0, %ecx
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; CHECK-NEXT: testb %sil, %sil
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; CHECK-NEXT: setzune %dl
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; CHECK-NEXT: testb %sil, %sil
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; CHECK-NEXT: je .LBB4_3
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; CHECK-NEXT: # %bb.2: # %bb1
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; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB4_1
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; CHECK-NEXT: .LBB4_3: # %bb2
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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bb:
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br label %bb1
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bb1:
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%phi = phi i32 [ 0, %bb ], [ %zext, %bb1 ]
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%phi2 = phi i32 [ 0, %bb ], [ %add3, %bb1 ]
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%load = load i32, ptr null, align 4
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%add = add i32 %load, %phi
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store i32 %add, ptr null, align 4
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%icmp = icmp ugt i32 %phi, %add
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%zext = zext i1 %icmp to i32
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%add3 = add i32 %phi2, %zext
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%icmp4 = icmp ult i32 %phi2, 0
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%and = and i1 %icmp, false
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br i1 %and, label %bb1, label %bb2
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bb2:
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ret i32 0
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}
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