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llvm-project/llvm/lib/Target/RISCV
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David Green abd2c07e39
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631) 
This does not alter much at the moment, but allows const pointers to be
passed as Op0 and Op1, simplifying later patches
2025-05-01 15:55:08 +01:00
..
AsmParser
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
Disassembler
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
GISel
[RISCV] Add new CondCode COND_CV_BEQIMM/COND_CV_BNEIMM for CV immediate branch (#135771)
2025-04-16 10:16:31 +08:00
MCA
Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)
2025-03-01 14:04:48 +09:00
MCTargetDesc
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCV.h
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCV.td
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVAsmPrinter.cpp
[RISCV] Rename VariantKind to Specifier
2025-03-20 22:25:57 -07:00
RISCVCallingConv.cpp
…
RISCVCallingConv.h
…
RISCVCallingConv.td
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
RISCVCodeGenPrepare.cpp
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
RISCVCombine.td
[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998)
2025-01-02 16:29:34 -08:00
RISCVConstantPoolValue.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)
2025-03-21 17:22:32 +08:00
RISCVFeatures.td
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
RISCVFrameLowering.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVGISel.td
[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)
2025-04-28 09:26:34 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrFormats.td
[RISCV] Support Load/Store Global assembler pseudos for Zilsd. (#134950)
2025-04-08 21:33:08 -07:00
RISCVInstrFormatsC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrFormatsV.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVInstrGISel.td
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
2024-11-11 20:59:21 -08:00
RISCVInstrInfo.cpp
[RISCV][NFC] Add missed // clang-format on
2025-05-01 13:37:49 +01:00
RISCVInstrInfo.h
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrInfo.td
[DAG] Use SDValue for PatFrag checks (#137519)
2025-05-01 08:58:59 +01:00
RISCVInstrInfoA.td
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
RISCVInstrInfoC.td
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
RISCVInstrInfoD.td
[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)
2025-03-27 07:45:42 -07:00
RISCVInstrInfoF.td
[RISCV] Use MnemonicAlias for 'fssr' and 'frsr'. NFC (#131877)
2025-03-18 14:04:45 -07:00
RISCVInstrInfoM.td
…
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Fix the comment for VALUVINoVm (#132730)
2025-03-24 17:49:53 +01:00
RISCVInstrInfoVPseudos.td
[RISCV] Use GPRMemZeroOffset instead of GPRMem in RISCVInstrInfoVPseudos.td. NFC
2025-04-09 17:07:01 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (#135727)
2025-04-27 19:10:02 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Remove unused tablegen multiclass. NFC
2025-04-30 15:07:45 -07:00
RISCVInstrInfoXAndes.td
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
RISCVInstrInfoXCV.td
[RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#136079)
2025-04-17 12:39:40 -07:00
RISCVInstrInfoXMips.td
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
RISCVInstrInfoXqccmp.td
[RISCV] Prefer RegList over Rlist in assembler. NFC
2025-04-04 09:37:52 -07:00
RISCVInstrInfoXqci.td
[RISCV] Add compress patterns for Xqcilo load/store instructions (#137758)
2025-04-30 14:29:49 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Add codegen support for ri.vinsert.v.x and ri.vextract.x.v (#136708)
2025-04-25 07:59:40 -07:00
RISCVInstrInfoXSf.td
[RISCV] Remove ParserMatchClass and DecoderMethod from an operand only used by pseudos. NFC
2025-03-27 15:07:29 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Move checking for constant 3/4 for XTHeadMemPair to the instruction matching stage. (#136165)
2025-04-17 21:03:58 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV][NFCI] Rationalize Immediate Definitions (#120718)
2024-12-21 09:47:07 +00:00
RISCVInstrInfoZa.td
[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)
2025-03-17 12:49:08 -07:00
RISCVInstrInfoZalasr.td
[TableGen][SelectionDAG][GISel][RISCV] Support IsNonExtLoad for IsAtomic PatFrags. (#137401)
2025-04-25 15:45:43 -07:00
RISCVInstrInfoZb.td
[RISCV] Support Zb*/P Shared Instructions (#127160)
2025-02-15 22:26:02 +08:00
RISCVInstrInfoZc.td
[RISCV] Rename Spimm to StackAdj in most places. NFC
2025-04-04 12:49:09 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
2025-04-08 17:53:39 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[RISCV] Correct the predicates for the flh/fsh InstAlias and assembler pseudos to include Zfbfmin. (#131920)
2025-03-18 17:55:36 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Remove unused MCOperandPredicate from simm12_lsb00000. NFC
2025-03-27 16:45:58 -07:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
[RISCV] Support Load/Store Global assembler pseudos for Zilsd. (#134950)
2025-04-08 21:33:08 -07:00
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)
2025-02-27 19:25:14 -08:00
RISCVInstrInfoZvk.td
[RISCV] Add vector hasAndNot to enable optimizations (#132438)
2025-03-26 10:40:00 +01:00
RISCVInstrInfoZvqdotq.td
[RISCV] Add assembler support for Zvqdotq. (#132118)
2025-03-20 08:38:15 -07:00
RISCVInstrPredicates.td
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Select (add x, C) -> (sub x, -C) if -C cheaper to materialize (#137309)
2025-04-28 10:14:12 +02:00
RISCVISelDAGToDAG.h
[RISCV] Select (add x, C) -> (sub x, -C) if -C cheaper to materialize (#137309)
2025-04-28 10:14:12 +02:00
RISCVISelLowering.cpp
[RISCV] Use early return to simplify VLA shuffle lowering [nfc]
2025-05-01 07:47:27 -07:00
RISCVISelLowering.h
[RISCV] Add codegen support for ri.vinsert.v.x and ri.vextract.x.v (#136708)
2025-04-25 07:59:40 -07:00
RISCVLandingPadSetup.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVLateBranchOpt.cpp
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVLoadStoreOptimizer.cpp
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMergeBaseOffset.cpp
[RISCV] Don't fold offsets into auipc if offset is larger than the reference global variable. (#135297)
2025-04-11 16:12:19 -07:00
RISCVMoveMerger.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVOptWInstrs.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVPfmCounters.td
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
[RISCV][NFC] Remove duplicate extensions from tt-ascalon-d8 CPU (#137865)
2025-04-29 14:19:51 -07:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Simplify how we find combinable cm.pop+ret. (#130204)
2025-03-06 21:55:47 -08:00
RISCVRedundantCopyElimination.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVRegisterInfo.cpp
[RISCV] Refine location size for segment spill and fill (#133268)
2025-03-28 07:06:17 -07:00
RISCVRegisterInfo.h
[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
2025-03-20 15:20:04 -04:00
RISCVRegisterInfo.td
[RISCV] Rename InvalidRegClassGPRX0->InvalidRegClassGPRNoX0. NFC
2025-04-18 23:46:04 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
2025-01-22 10:37:01 -08:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVSchedSiFiveP400.td
[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)
2025-03-17 15:29:36 -07:00
RISCVSchedSiFiveP500.td
[RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165)
2025-03-27 11:00:07 -07:00
RISCVSchedSiFiveP600.td
[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)
2025-03-17 15:29:36 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC
2025-01-21 18:00:52 -08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedTTAscalonD8.td
[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)
2024-12-20 15:30:17 -05:00
RISCVSchedule.td
[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh
2024-12-31 17:22:08 +08:00
RISCVScheduleV.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSubtarget.cpp
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
RISCVSubtarget.h
[RISCV] Enable prefetching writes (#130561)
2025-03-11 11:39:21 +08:00
RISCVSystemOperands.td
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVTargetMachine.cpp
[TTI] Simplify implementation (NFCI) (#136674)
2025-04-26 15:25:40 +03:00
RISCVTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
RISCVTargetObjectFile.cpp
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetTransformInfo.cpp
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
RISCVTargetTransformInfo.h
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296)
2025-03-05 08:56:09 -08:00
RISCVVectorPeephole.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Look through PHI instructions (#132236)
2025-03-24 09:26:09 -04:00
RISCVVMV0Elimination.cpp
[RISCV] Remove skipFunction from RISCVVMV0Elimination. (#136080)
2025-04-17 07:34:38 -07:00
RISCVZacasABIFix.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00