Paul Walker 0fab741a26

[LLVM][CodeGen][AArch64] Don't scalarise v8{f16,bf16} vsetcc operations. (#135398) ...

I have also removed custom promotion code for the v4{f16,bf16} cases
because the same common code can be used.

2025-05-01 13:06:39 +01:00

..

AArch64

[LLVM][CodeGen][AArch64] Don't scalarise v8{f16,bf16} vsetcc operations. (#135398)

2025-05-01 13:06:39 +01:00

AMDGPU

AMDGPU: Add gfx950 cost model tests for minimum and maximum (#130029)

2025-03-06 17:27:36 +07:00

ARM

[CostModel][ARM]Adjust cost of muls in (U/S)MLAL and patterns (#122713)

2025-03-19 12:25:44 +00:00

NVPTX

[NVPTX] Improve modeling of inline PTX (#130675)

2025-03-25 13:46:16 -07:00

PowerPC

[PowerPC] Update data layout aligment of i128 to 16 (#118004)

2024-12-09 18:02:24 -05:00

RISCV

[CostModel] Remove some negative costs. (#135533)

2025-04-28 21:08:14 +01:00

SystemZ

Support z17 processor name and scheduler description (#135254)

2025-04-11 00:20:58 +02:00

X86

[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)

2025-04-01 14:27:11 +01:00

free-intrinsics-datalayout.ll

[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)

2025-04-01 14:27:11 +01:00

free-intrinsics-no_info.ll

[DebugInfo][RemoveDIs] Remove debug-intrinsic printing cmdline options (#131855)

2025-04-01 14:27:11 +01:00

no_info.ll

…