94d374ab6c
Compare sinking is selectable based on the result of
hasMultipleConditionRegisters. This function is too coarse grained by
not taking into account the differences between scalar and vector
compares. This PR extends the interface to take an EVT to allow finer
control.
The new interface is used by AArch64 to disable sinking of scalable
vector compares, but with isProfitableToSinkOperands updated to maintain
the cases that are specifically tested.
634 lines
23 KiB
C++
634 lines
23 KiB
C++
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class AMDGPUMachineFunction;
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class AMDGPUSubtarget;
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struct ArgDescriptor;
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class AMDGPUTargetLowering : public TargetLowering {
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private:
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const AMDGPUSubtarget *Subtarget;
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/// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
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/// legalized from a smaller type VT. Need to match pre-legalized type because
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/// the generic legalization inserts the add/sub between the select and
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/// compare.
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SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
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public:
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/// \returns The minimum number of bits needed to store the value of \Op as an
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/// unsigned integer. Truncating to this size and then zero-extending to the
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/// original size will not change the value.
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static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
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/// \returns The minimum number of bits needed to store the value of \Op as a
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/// signed integer. Truncating to this size and then sign-extending to the
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/// original size will not change the value.
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static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
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protected:
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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/// Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
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static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
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SDNodeFlags Flags);
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SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
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SDNodeFlags Flags) const;
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SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
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std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
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const SDLoc SL, SDValue Op,
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SDNodeFlags Flags) const;
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SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
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bool IsLog10, SDNodeFlags Flags) const;
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SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
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SDNodeFlags Flags) const;
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SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
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SDNodeFlags Flags) const;
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SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerF64ToF16Safe(SDValue Src, const SDLoc &DL,
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SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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protected:
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bool shouldCombineMemoryType(EVT VT) const;
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SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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uint32_t ValLo, uint32_t ValHi) const;
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SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
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SDValue RHS, DAGCombinerInfo &DCI) const;
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SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
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SDValue N) const;
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SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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TargetLowering::NegatibleCost
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getConstantNegateCost(const ConstantFPSDNode *C) const;
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bool isConstantCostlierToNegate(SDValue N) const;
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bool isConstantCheaperToNegate(SDValue N) const;
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SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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/// Return 64-bit value Op as two 32-bit integers.
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std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
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SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
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/// Split a vector type into two parts. The first part is a power of two
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/// vector. The second part is whatever is left over, and is a scalar if it
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/// would otherwise be a 1-vector.
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std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
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/// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
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/// scalar.
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std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
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const EVT &LoVT, const EVT &HighVT,
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SelectionDAG &DAG) const;
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/// Split a vector load into 2 loads of half the vector.
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SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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/// Widen a suitably aligned v3 load. For all other cases, split the input
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/// vector load.
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SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
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/// Split a vector store into 2 stores of half the vector.
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SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
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void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Results) const;
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void analyzeFormalArgumentsCompute(
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CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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public:
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AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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bool mayIgnoreSignedZero(SDValue Op) const;
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static inline SDValue stripBitcast(SDValue Val) {
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return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
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}
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static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
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static bool allUsesHaveSourceMods(const SDNode *N,
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unsigned CostThreshold = 4);
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bool isFAbsFree(EVT VT) const override;
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bool isFNegFree(EVT VT) const override;
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bool isTruncateFree(EVT Src, EVT Dest) const override;
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bool isTruncateFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
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bool LegalOperations, bool ForCodeSize,
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NegatibleCost &Cost,
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unsigned Depth) const override;
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bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
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bool isDesirableToCommuteWithShift(const SDNode *N,
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CombineLevel Level) const override;
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EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
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ISD::NodeType ExtendKind) const override;
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unsigned getVectorIdxWidth(const DataLayout &) const override;
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bool isSelectSupported(SelectSupportKind) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override;
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bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT,
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std::optional<unsigned> ByteOffset) const override;
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bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
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const MachineMemOperand &MMO) const final;
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bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
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unsigned NumElem,
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unsigned AS) const override;
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bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
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bool isCheapToSpeculateCttz(Type *Ty) const override;
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bool isCheapToSpeculateCtlz(Type *Ty) const override;
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bool isSDNodeAlwaysUniform(const SDNode *N) const override;
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// FIXME: This hook should not exist
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AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override {
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return AtomicExpansionKind::None;
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}
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AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
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return AtomicExpansionKind::None;
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}
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AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override {
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return AtomicExpansionKind::None;
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}
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static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
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static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue addTokenForArgument(SDValue Chain,
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SelectionDAG &DAG,
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MachineFrameInfo &MFI,
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int ClobberedFI) const;
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SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals,
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StringRef Reason) const;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
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SDValue RHS, SDValue True, SDValue False,
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SDValue CC, DAGCombinerInfo &DCI) const;
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SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
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SDValue RHS, SDValue True, SDValue False,
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SDValue CC, DAGCombinerInfo &DCI) const;
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const char* getTargetNodeName(unsigned Opcode) const override;
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// FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
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// AMDGPU. Commit r319036,
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// (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
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// turned on MergeConsecutiveStores() before Instruction Selection for all
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// targets. Enough AMDGPU compiles go into an infinite loop (
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// MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
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// MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
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// now.
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bool mergeStoresAfterLegalization(EVT) const override { return false; }
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bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
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return true;
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}
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SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps, bool &UseOneConstNR,
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bool Reciprocal) const override;
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SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
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int &RefinementSteps) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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SelectionDAG &DAG) const = 0;
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/// Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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unsigned computeNumSignBitsForTargetInstr(GISelValueTracking &Analysis,
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Register R,
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const APInt &DemandedElts,
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const MachineRegisterInfo &MRI,
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unsigned Depth = 0) const override;
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bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
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const SelectionDAG &DAG, bool SNaN = false,
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unsigned Depth = 0) const override;
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bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
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Register N1) const override;
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/// Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
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/// a copy from the register.
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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Register Reg, EVT VT,
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const SDLoc &SL,
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bool RawReg = false) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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Register Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
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}
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// Returns the raw live in register rather than a copy from it.
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SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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Register Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
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}
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/// Similar to CreateLiveInRegister, except value maybe loaded from a stack
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/// slot rather than passed in a register.
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SDValue loadStackInputValue(SelectionDAG &DAG,
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EVT VT,
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const SDLoc &SL,
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int64_t Offset) const;
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SDValue storeStackInputValue(SelectionDAG &DAG,
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const SDLoc &SL,
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SDValue Chain,
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SDValue ArgVal,
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int64_t Offset) const;
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SDValue loadInputValue(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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EVT VT, const SDLoc &SL,
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const ArgDescriptor &Arg) const;
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enum ImplicitParameter {
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FIRST_IMPLICIT,
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PRIVATE_BASE,
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SHARED_BASE,
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QUEUE_PTR,
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};
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/// Helper function that returns the byte offset of the given
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/// type of implicit parameter.
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uint32_t getImplicitParameterOffset(const MachineFunction &MF,
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const ImplicitParameter Param) const;
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uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
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const ImplicitParameter Param) const;
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MVT getFenceOperandTy(const DataLayout &DL) const override {
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return MVT::i32;
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}
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bool hasMultipleConditionRegisters(EVT VT) const override {
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// FIXME: This is only partially true. If we have to do vector compares, any
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// SGPR pair can be a condition register. If we have a uniform condition, we
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// are better off doing SALU operations, where there is only one SCC. For
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// now, we don't have a way of knowing during instruction selection if a
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// condition will be uniform and we always use vector compares. Assume we
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// are using vector compares until that is fixed.
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return true;
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}
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};
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namespace AMDGPUISD {
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enum NodeType : unsigned {
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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// Function call.
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CALL,
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TC_RETURN,
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TC_RETURN_GFX,
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TC_RETURN_CHAIN,
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TC_RETURN_CHAIN_DVGPR,
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TRAP,
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// Masked control flow nodes.
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IF,
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ELSE,
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LOOP,
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// A uniform kernel return that terminates the wavefront.
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ENDPGM,
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// s_endpgm, but we may want to insert it in the middle of the block.
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ENDPGM_TRAP,
|
|
|
|
// "s_trap 2" equivalent on hardware that does not support it.
|
|
SIMULATED_TRAP,
|
|
|
|
// Return to a shader part's epilog code.
|
|
RETURN_TO_EPILOG,
|
|
|
|
// Return with values from a non-entry function.
|
|
RET_GLUE,
|
|
|
|
// Convert a unswizzled wave uniform stack address to an address compatible
|
|
// with a vector offset for use in stack access.
|
|
WAVE_ADDRESS,
|
|
|
|
DWORDADDR,
|
|
FRACT,
|
|
|
|
/// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
|
|
/// modifier behavior with dx10_enable.
|
|
CLAMP,
|
|
|
|
// This is SETCC with the full mask result which is used for a compare with a
|
|
// result bit per item in the wavefront.
|
|
SETCC,
|
|
|
|
DENORM_MODE,
|
|
|
|
// FP ops with input and output chain.
|
|
FMA_W_CHAIN,
|
|
FMUL_W_CHAIN,
|
|
|
|
// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
|
|
// Denormals handled on some parts.
|
|
COS_HW,
|
|
SIN_HW,
|
|
FMAX_LEGACY,
|
|
FMIN_LEGACY,
|
|
|
|
FMAX3,
|
|
SMAX3,
|
|
UMAX3,
|
|
FMIN3,
|
|
SMIN3,
|
|
UMIN3,
|
|
FMED3,
|
|
SMED3,
|
|
UMED3,
|
|
FMAXIMUM3,
|
|
FMINIMUM3,
|
|
FDOT2,
|
|
URECIP,
|
|
DIV_SCALE,
|
|
DIV_FMAS,
|
|
DIV_FIXUP,
|
|
// For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
|
|
// treated as an illegal operation.
|
|
FMAD_FTZ,
|
|
|
|
// RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
|
|
// For f64, max error 2^29 ULP, handles denormals.
|
|
RCP,
|
|
RSQ,
|
|
RCP_LEGACY,
|
|
RCP_IFLAG,
|
|
|
|
// log2, no denormal handling for f32.
|
|
LOG,
|
|
|
|
// exp2, no denormal handling for f32.
|
|
EXP,
|
|
|
|
FMUL_LEGACY,
|
|
RSQ_CLAMP,
|
|
FP_CLASS,
|
|
DOT4,
|
|
CARRY,
|
|
BORROW,
|
|
BFE_U32, // Extract range of bits with zero extension to 32-bits.
|
|
BFE_I32, // Extract range of bits with sign extension to 32-bits.
|
|
BFI, // (src0 & src1) | (~src0 & src2)
|
|
BFM, // Insert a range of bits into a 32-bit word.
|
|
FFBH_U32, // ctlz with -1 if input is zero.
|
|
FFBH_I32,
|
|
FFBL_B32, // cttz with -1 if input is zero.
|
|
MUL_U24,
|
|
MUL_I24,
|
|
MULHI_U24,
|
|
MULHI_I24,
|
|
MAD_U24,
|
|
MAD_I24,
|
|
MAD_U64_U32,
|
|
MAD_I64_I32,
|
|
PERM,
|
|
TEXTURE_FETCH,
|
|
R600_EXPORT,
|
|
CONST_ADDRESS,
|
|
REGISTER_LOAD,
|
|
REGISTER_STORE,
|
|
|
|
// These cvt_f32_ubyte* nodes need to remain consecutive and in order.
|
|
CVT_F32_UBYTE0,
|
|
CVT_F32_UBYTE1,
|
|
CVT_F32_UBYTE2,
|
|
CVT_F32_UBYTE3,
|
|
|
|
// Convert two float 32 numbers into a single register holding two packed f16
|
|
// with round to zero.
|
|
CVT_PKRTZ_F16_F32,
|
|
CVT_PKNORM_I16_F32,
|
|
CVT_PKNORM_U16_F32,
|
|
CVT_PK_I16_I32,
|
|
CVT_PK_U16_U32,
|
|
|
|
// Same as the standard node, except the high bits of the resulting integer
|
|
// are known 0.
|
|
FP_TO_FP16,
|
|
|
|
/// This node is for VLIW targets and it is used to represent a vector
|
|
/// that is stored in consecutive registers with the same channel.
|
|
/// For example:
|
|
/// |X |Y|Z|W|
|
|
/// T0|v.x| | | |
|
|
/// T1|v.y| | | |
|
|
/// T2|v.z| | | |
|
|
/// T3|v.w| | | |
|
|
BUILD_VERTICAL_VECTOR,
|
|
/// Pointer to the start of the shader's constant data.
|
|
CONST_DATA_PTR,
|
|
PC_ADD_REL_OFFSET,
|
|
PC_ADD_REL_OFFSET64,
|
|
LDS,
|
|
|
|
DUMMY_CHAIN,
|
|
|
|
FIRST_MEMORY_OPCODE,
|
|
LOAD_D16_HI = FIRST_MEMORY_OPCODE,
|
|
LOAD_D16_LO,
|
|
LOAD_D16_HI_I8,
|
|
LOAD_D16_HI_U8,
|
|
LOAD_D16_LO_I8,
|
|
LOAD_D16_LO_U8,
|
|
|
|
STORE_MSKOR,
|
|
TBUFFER_STORE_FORMAT,
|
|
TBUFFER_STORE_FORMAT_D16,
|
|
TBUFFER_LOAD_FORMAT,
|
|
TBUFFER_LOAD_FORMAT_D16,
|
|
DS_ORDERED_COUNT,
|
|
ATOMIC_CMP_SWAP,
|
|
BUFFER_LOAD,
|
|
BUFFER_LOAD_UBYTE,
|
|
BUFFER_LOAD_USHORT,
|
|
BUFFER_LOAD_BYTE,
|
|
BUFFER_LOAD_SHORT,
|
|
BUFFER_LOAD_TFE,
|
|
BUFFER_LOAD_UBYTE_TFE,
|
|
BUFFER_LOAD_USHORT_TFE,
|
|
BUFFER_LOAD_BYTE_TFE,
|
|
BUFFER_LOAD_SHORT_TFE,
|
|
BUFFER_LOAD_FORMAT,
|
|
BUFFER_LOAD_FORMAT_TFE,
|
|
BUFFER_LOAD_FORMAT_D16,
|
|
SBUFFER_LOAD,
|
|
SBUFFER_LOAD_BYTE,
|
|
SBUFFER_LOAD_UBYTE,
|
|
SBUFFER_LOAD_SHORT,
|
|
SBUFFER_LOAD_USHORT,
|
|
SBUFFER_PREFETCH_DATA,
|
|
BUFFER_STORE,
|
|
BUFFER_STORE_BYTE,
|
|
BUFFER_STORE_SHORT,
|
|
BUFFER_STORE_FORMAT,
|
|
BUFFER_STORE_FORMAT_D16,
|
|
BUFFER_ATOMIC_SWAP,
|
|
BUFFER_ATOMIC_ADD,
|
|
BUFFER_ATOMIC_SUB,
|
|
BUFFER_ATOMIC_SMIN,
|
|
BUFFER_ATOMIC_UMIN,
|
|
BUFFER_ATOMIC_SMAX,
|
|
BUFFER_ATOMIC_UMAX,
|
|
BUFFER_ATOMIC_AND,
|
|
BUFFER_ATOMIC_OR,
|
|
BUFFER_ATOMIC_XOR,
|
|
BUFFER_ATOMIC_INC,
|
|
BUFFER_ATOMIC_DEC,
|
|
BUFFER_ATOMIC_CMPSWAP,
|
|
BUFFER_ATOMIC_CSUB,
|
|
BUFFER_ATOMIC_FADD,
|
|
BUFFER_ATOMIC_FMIN,
|
|
BUFFER_ATOMIC_FMAX,
|
|
BUFFER_ATOMIC_COND_SUB_U32,
|
|
LAST_MEMORY_OPCODE = BUFFER_ATOMIC_COND_SUB_U32,
|
|
|
|
// Set up a whole wave function.
|
|
WHOLE_WAVE_SETUP,
|
|
|
|
// Return from a whole wave function.
|
|
WHOLE_WAVE_RETURN,
|
|
};
|
|
|
|
} // End namespace AMDGPUISD
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif
|