ae56b6712d
Add entries for_stack_chk_guard, __ssp_canary_word, __security_cookie, and __guard_local. As far as I can tell these are all just different names for the same shaped functionality on different systems. These aren't really functions, but special global variable names. They should probably be treated the same way; all the same contexts that need to know about emittable function names also need to know about this. This avoids a special case check in IRSymtab. This isn't a complete change, there's a lot more cleanup which should be done. The stack protector configuration system is a complete mess. There are multiple overlapping controls, used in 3 different places. Some of the target control implementations overlap with conditions used in the emission points, and some use correlated but not identical conditions in different contexts. i.e. useLoadStackGuardNode, getIRStackGuard, getSSPStackGuardCheck and insertSSPDeclarations are all used in inconsistent ways so I don't know if I've tracked the intention of the system correctly. The PowerPC test change is a bug fix on linux. Previously the manual conditions were based around !isOSOpenBSD, which is not the condition where __stack_chk_guard are used. Now getSDagStackGuard returns the proper global reference, resulting in LOAD_STACK_GUARD getting a MachineMemOperand which allows scheduling.
To-do
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* Keep the address of the constant pool in a register instead of forming its
address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions. It's
not clear how to write a pattern for this though:
float %t1(int %a, int* %p) {
%C = seteq int %a, 0
br bool %C, label %T, label %F
T:
store int 123, int* %p
br label %F
F:
ret float undef
}
codegens to this:
t1:
save -96, %o6, %o6
1) subcc %i0, 0, %l0
1) bne .LBBt1_2 ! F
nop
.LBBt1_1: ! T
or %g0, 123, %l0
st %l0, [%i1]
.LBBt1_2: ! F
restore %g0, %g0, %g0
retl
nop
1) should be replaced with a brz in V9 mode.
* Same as above, but emit conditional move on register zero (p192) in V9
mode. Testcase:
int %t1(int %a, int %b) {
%C = seteq int %a, 0
%D = select bool %C, int %a, int %b
ret int %D
}
* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
with the Y register, if they are faster.
* Codegen bswap(load)/store(bswap) -> load/store ASI
* Implement frame pointer elimination, e.g. eliminate save/restore for
leaf fns.
* Fill delay slots
* Use %g0 directly to materialize 0. No instruction is required.