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llvm-project/llvm/lib/CodeGen/SelectionDAG
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Alex MacLean ad39049ec4
[DAGCombiner] Attempt to fold 'add' nodes to funnel-shift or rotate (#125612) 
Almost all of the rotate idioms that are valid for an 'or' are also
valid when the halves are combined with an 'add'. Further, many of these
cases are not handled by common bits tracking meaning that the 'add' is
not converted to a 'disjoint or'.
2025-04-04 15:39:24 -07:00
..
CMakeLists.txt
…
DAGCombiner.cpp
[DAGCombiner] Attempt to fold 'add' nodes to funnel-shift or rotate (#125612)
2025-04-04 15:39:24 -07:00
FastISel.cpp
[SelectionDAG] Not issue TRAP node if naked function (#132147)
2025-03-20 18:18:03 -07:00
FunctionLoweringInfo.cpp
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
InstrEmitter.cpp
[CodeGen] Use llvm::append_range (NFC) (#133603)
2025-03-29 16:53:02 -07:00
InstrEmitter.h
[NFC] Reapply 3f37c517f, SmallDenseMap speedups
2024-09-26 10:49:29 +01:00
LegalizeDAG.cpp
Port NVPTXTargetLowering::LowerCONCAT_VECTORS to SelectionDAG (#120030)
2025-03-27 07:40:35 +07:00
LegalizeFloatTypes.cpp
DAG: Fix promote of half freeze (#131844)
2025-03-19 18:30:34 +07:00
LegalizeIntegerTypes.cpp
[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)
2025-02-18 09:08:47 +00:00
LegalizeTypes.cpp
[SelectionDAG] Preserve fast math flags when legalizing/promoting (#130124)
2025-03-07 14:46:32 +00:00
LegalizeTypes.h
DAG: Fix promote of half freeze (#131844)
2025-03-19 18:30:34 +07:00
LegalizeTypesGeneric.cpp
[SelectionDAG] Use the nuw flag when expanding loads. (#119288)
2024-12-10 06:28:09 -08:00
LegalizeVectorOps.cpp
[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800)
2025-02-28 23:13:30 +08:00
LegalizeVectorTypes.cpp
[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)
2025-02-18 09:08:47 +00:00
MatchContext.h
[DAG][RISCV] Use vp.<binop> when widening illegal types for binops which can trap (#105214)
2024-08-20 13:51:10 -07:00
ResourcePriorityQueue.cpp
…
ScheduleDAGFast.cpp
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
ScheduleDAGRRList.cpp
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
ScheduleDAGSDNodes.cpp
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
ScheduleDAGSDNodes.h
[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)
2025-01-23 09:16:09 +00:00
ScheduleDAGVLIW.cpp
[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)
2025-01-23 09:16:09 +00:00
SDNodeDbgValue.h
[CodeGen] Use llvm::append_range (NFC) (#133603)
2025-03-29 16:53:02 -07:00
SelectionDAG.cpp
Ensure KnownBits passed when calculating from range md has right size (#132985)
2025-04-03 10:17:14 +07:00
SelectionDAGAddressAnalysis.cpp
…
SelectionDAGBuilder.cpp
[CodeGen] Simplify code using TypeSize overloads of getMachineMemOperand [nfc]
2025-03-27 11:47:51 -07:00
SelectionDAGBuilder.h
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
SelectionDAGDumper.cpp
[SelectionDAG] Use Register and MCRegister. NFC
2025-03-02 22:33:25 -08:00
SelectionDAGISel.cpp
[SDAG] Use index type size for offset accumulation
2025-04-04 15:59:19 +02:00
SelectionDAGPrinter.cpp
[llvm][CodeGen] Avoid 'raw_string_ostream::str' (NFC) (#97318)
2024-07-01 21:52:37 -04:00
SelectionDAGTargetInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
StatepointLowering.cpp
[CodeGen] Avoid repeated hash lookups (NFC) (#131722)
2025-03-18 00:26:59 -07:00
StatepointLowering.h
…
TargetLowering.cpp
[SelectionDAG] Use SimplifyDemandedBits from SimplifyDemandedVectorElts Bitcast. (#133717)
2025-04-03 11:14:08 +01:00