Jim Lin 9c02d66255

[LegalizeTypes][VP] Teach isVPBinaryOp to recognize vp.sadd/saddu/ssub/ssubu.sat (#154047) ...

Those vp intrinsics also are vp binary operations. Similar to
https://reviews.llvm.org/D135753.

2025-08-18 13:10:00 +08:00

..

AArch64

[AArch64] Adjust the scheduling info of SVE FCMP on Cortex-A510. (#153810)

2025-08-15 15:45:33 +01:00

AMDGPU

AMDGPU: Fix crash in rewrite AGPR copy MFMA pass on dead valnos (#153915)

2025-08-16 23:09:23 +09:00

ARC

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ARM

[ARM] Protect against odd sized vectors in isVTRNMask and friends (#153413)

2025-08-13 20:57:46 +01:00

AVR

[Test] Add and update tests for lrint/llrint (NFC) (#152662)

2025-08-12 09:56:51 +09:00

BPF

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

CSKY

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DirectX

[DirectX] Add GlobalDCE pass after finalize linkage pass in DirectX backend (#151071)

2025-08-15 10:45:34 -07:00

Generic

[Arm64EC] Add support for half (#152843)

2025-08-12 14:15:52 -07:00

Hexagon

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

Inputs

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Lanai

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LoongArch

[LoongArch] Optimize inserting extracted element for v4i64/v8i32 (#152629)

2025-08-14 17:06:50 +08:00

M68k

[M68k] Add anyext patterns for PCD addressing mode (#150356)

2025-08-16 23:33:47 +00:00

Mips

[Mips] Add frexpl and sincosl to f128 libcall list

2025-08-15 12:45:05 +02:00

MIR

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

MLRegAlloc

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MSP430

[Test] Add and update tests for lrint/llrint (NFC) (#152662)

2025-08-12 09:56:51 +09:00

NVPTX

[NVPTX] Do not mark move of global address as cheap enabling more CSE (#153730)

2025-08-15 10:17:34 -07:00

PowerPC

[llvm][LICM] Limit multi-use BOAssociation to FP and Vector (#149829)

2025-08-14 11:56:55 +01:00

RISCV

[LegalizeTypes][VP] Teach isVPBinaryOp to recognize vp.sadd/saddu/ssub/ssubu.sat (#154047)

2025-08-18 13:10:00 +08:00

SPARC

[SPARC] Use FMA instructions when we have UA2007 (#148434)

2025-08-12 22:46:00 +07:00

SPIRV

[SPIRV] Create a new OpSelect selector and fix register types. (#152311)

2025-08-12 17:43:30 -04:00

SystemZ

[SystemZ] Allow forming overflow op for i128 (#153557)

2025-08-14 16:15:22 +02:00

Thumb

[ARM] Have custom lowering for ucmp and scmp (#149315)

2025-08-08 06:51:18 +01:00

Thumb2

[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)

2025-08-13 10:41:44 +08:00

VE

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

WebAssembly

[WebAssembly] Reapply #149461 with correct CondCode in combine of SETCC (#153703)

2025-08-15 12:06:47 -07:00

WinCFGuard

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WinEH

Fix Windows EH IP2State tables (remove +1 bias) (#144745)

2025-07-22 09:18:13 -07:00

X86

[X86] Explicitly widen larger than v4f16 to the legal v8f16 (NFC) (#153839)

2025-08-17 19:15:10 +00:00

XCore

XCore: Fix broken check lines in test

2025-08-04 08:40:48 +09:00

Xtensa

[Xtensa] Add esp32/esp8266 cpus implementation. (#152409)

2025-08-12 15:17:36 +03:00