2c7d40b2f0
Follow-up to dfca6c0d3bf9d1a056 to extend isUnrolled handle any unrolled VPlan, which means there's a single UF, but it will be > 1 if unrolling took place.
77 lines
3.7 KiB
LLVM
77 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -passes=loop-vectorize -force-vector-interleave=2 | FileCheck %s
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; Demonstrate a case where we unroll a loop, but don't vectorize it.
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; The original loop runs stores in the latch block on iterations 0 to 1022,
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; and exits when %indvars.iv = 1023. (That is, it actually runs the stores
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; for an odd number of iterations.) If we unroll by two in the "vector.body"
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; loop, we must exit to the epilogue on iteration with %indvars.iv = 1022 to
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; avoid an out of bounds access.
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define void @test(ptr %data) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i64 [[TMP1]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i64 [[TMP2]], 1
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; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[TMP3]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds double, ptr [[DATA:%.*]], i64 [[TMP4]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP6]], align 8
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; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP7]], align 8
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; CHECK-NEXT: [[TMP10:%.*]] = fneg double [[TMP8]]
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; CHECK-NEXT: [[TMP11:%.*]] = fneg double [[TMP9]]
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; CHECK-NEXT: store double [[TMP10]], ptr [[TMP6]], align 8
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; CHECK-NEXT: store double [[TMP11]], ptr [[TMP7]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1022
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1022, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_LATCH:%.*]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 1024
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_LATCH]]
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; CHECK: for.latch:
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; CHECK-NEXT: [[T15:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[T16:%.*]] = or disjoint i64 [[T15]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[DATA]], i64 [[T16]]
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; CHECK-NEXT: [[T17:%.*]] = load double, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[T17]]
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; CHECK-NEXT: store double [[FNEG]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: br label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.latch ]
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond.not, label %for.end, label %for.latch
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for.latch:
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%t15 = shl nuw nsw i64 %indvars.iv, 1
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%t16 = or disjoint i64 %t15, 1
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%arrayidx = getelementptr inbounds double, ptr %data, i64 %t16
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%t17 = load double, ptr %arrayidx, align 8
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%fneg = fneg double %t17
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store double %fneg, ptr %arrayidx, align 8
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br label %for.body
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for.end:
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ret void
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}
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