cd60ee9d6e
Similar to #141261. These aren't easy to test without write MIR tests in areas we don't currently have tests. I'm not sure we use X0_Pair anywhere today. I'm going to try to migrate RISCVMakeCompressible to use copyToReg so we can share that code instead of basically duplicating it. I'm still concerned that target independent code may fold an extract_subreg operation and get an incorrect register if we do start using X0_Pair. We may have to special case dummy_reg_pair_with_x0 in the encoder and printer to be safe.
670 lines
24 KiB
C++
670 lines
24 KiB
C++
//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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using namespace llvm;
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#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
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#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
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namespace {
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class RISCVExpandPseudo : public MachineFunctionPass {
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public:
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const RISCVSubtarget *STI;
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const RISCVInstrInfo *TII;
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static char ID;
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RISCVExpandPseudo() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned Opcode);
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bool expandMV_FPR16INX(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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bool expandMV_FPR32INX(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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#ifndef NDEBUG
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unsigned getInstSizeInBytes(const MachineFunction &MF) const {
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unsigned Size = 0;
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for (auto &MBB : MF)
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for (auto &MI : MBB)
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Size += TII->getInstSizeInBytes(MI);
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return Size;
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}
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#endif
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};
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char RISCVExpandPseudo::ID = 0;
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bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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STI = &MF.getSubtarget<RISCVSubtarget>();
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TII = STI->getInstrInfo();
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#ifndef NDEBUG
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const unsigned OldSize = getInstSizeInBytes(MF);
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#endif
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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#ifndef NDEBUG
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const unsigned NewSize = getInstSizeInBytes(MF);
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assert(OldSize >= NewSize);
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#endif
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return Modified;
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}
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bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
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// expanded instructions for each pseudo is correct in the Size field of the
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// tablegen definition for the pseudo.
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switch (MBBI->getOpcode()) {
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case RISCV::PseudoMV_FPR16INX:
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return expandMV_FPR16INX(MBB, MBBI);
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case RISCV::PseudoMV_FPR32INX:
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return expandMV_FPR32INX(MBB, MBBI);
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case RISCV::PseudoRV32ZdinxSD:
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return expandRV32ZdinxStore(MBB, MBBI);
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case RISCV::PseudoRV32ZdinxLD:
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return expandRV32ZdinxLoad(MBB, MBBI);
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case RISCV::PseudoCCMOVGPRNoX0:
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case RISCV::PseudoCCMOVGPR:
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case RISCV::PseudoCCADD:
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case RISCV::PseudoCCSUB:
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case RISCV::PseudoCCAND:
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case RISCV::PseudoCCOR:
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case RISCV::PseudoCCXOR:
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case RISCV::PseudoCCADDW:
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case RISCV::PseudoCCSUBW:
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case RISCV::PseudoCCSLL:
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case RISCV::PseudoCCSRL:
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case RISCV::PseudoCCSRA:
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case RISCV::PseudoCCADDI:
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case RISCV::PseudoCCSLLI:
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case RISCV::PseudoCCSRLI:
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case RISCV::PseudoCCSRAI:
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case RISCV::PseudoCCANDI:
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case RISCV::PseudoCCORI:
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case RISCV::PseudoCCXORI:
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case RISCV::PseudoCCSLLW:
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case RISCV::PseudoCCSRLW:
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case RISCV::PseudoCCSRAW:
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case RISCV::PseudoCCADDIW:
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case RISCV::PseudoCCSLLIW:
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case RISCV::PseudoCCSRLIW:
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case RISCV::PseudoCCSRAIW:
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case RISCV::PseudoCCANDN:
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case RISCV::PseudoCCORN:
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case RISCV::PseudoCCXNOR:
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return expandCCOp(MBB, MBBI, NextMBBI);
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case RISCV::PseudoVMCLR_M_B1:
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case RISCV::PseudoVMCLR_M_B2:
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case RISCV::PseudoVMCLR_M_B4:
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case RISCV::PseudoVMCLR_M_B8:
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case RISCV::PseudoVMCLR_M_B16:
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case RISCV::PseudoVMCLR_M_B32:
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case RISCV::PseudoVMCLR_M_B64:
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// vmclr.m vd => vmxor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
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case RISCV::PseudoVMSET_M_B1:
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case RISCV::PseudoVMSET_M_B2:
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case RISCV::PseudoVMSET_M_B4:
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case RISCV::PseudoVMSET_M_B8:
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case RISCV::PseudoVMSET_M_B16:
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case RISCV::PseudoVMSET_M_B32:
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case RISCV::PseudoVMSET_M_B64:
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// vmset.m vd => vmxnor.mm vd, vd, vd
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return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
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case RISCV::PseudoReadVLENBViaVSETVLIX0:
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return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
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}
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return false;
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}
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bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MF->insert(++MBB.getIterator(), TrueBB);
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MF->insert(++TrueBB->getIterator(), MergeBB);
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// We want to copy the "true" value when the condition is true which means
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// we need to invert the branch condition to jump over TrueBB when the
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// condition is false.
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auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
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CC = RISCVCC::getOppositeBranchCondition(CC);
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// Insert branch instruction.
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BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
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.addReg(MI.getOperand(1).getReg())
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.addReg(MI.getOperand(2).getReg())
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.addMBB(MergeBB);
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Register DestReg = MI.getOperand(0).getReg();
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assert(MI.getOperand(4).getReg() == DestReg);
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if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
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MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
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// Add MV.
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BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
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.add(MI.getOperand(5))
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.addImm(0);
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} else {
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unsigned NewOpc;
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
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case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
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case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
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case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
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case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
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case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
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case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
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case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
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case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
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case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
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case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
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case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
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case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
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case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
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case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
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case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
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case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
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case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
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case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
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case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
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case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
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case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
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case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
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case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
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case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
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case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
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case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
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}
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BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
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.add(MI.getOperand(5))
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.add(MI.getOperand(6));
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}
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TrueBB->addSuccessor(MergeBB);
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MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
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MergeBB->transferSuccessors(&MBB);
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MBB.addSuccessor(TrueBB);
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MBB.addSuccessor(MergeBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Make sure live-ins are correctly attached to this new basic block.
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LivePhysRegs LiveRegs;
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computeAndAddLiveIns(LiveRegs, *TrueBB);
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computeAndAddLiveIns(LiveRegs, *MergeBB);
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return true;
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}
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bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Opcode) {
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DebugLoc DL = MBBI->getDebugLoc();
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Register DstReg = MBBI->getOperand(0).getReg();
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const MCInstrDesc &Desc = TII->get(Opcode);
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BuildMI(MBB, MBBI, DL, Desc, DstReg)
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.addReg(DstReg, RegState::Undef)
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.addReg(DstReg, RegState::Undef);
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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DebugLoc DL = MBBI->getDebugLoc();
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const TargetRegisterInfo *TRI = STI->getRegisterInfo();
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Register DstReg = TRI->getMatchingSuperReg(
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MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
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Register SrcReg = TRI->getMatchingSuperReg(
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MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
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.addImm(0);
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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DebugLoc DL = MBBI->getDebugLoc();
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const TargetRegisterInfo *TRI = STI->getRegisterInfo();
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Register DstReg = TRI->getMatchingSuperReg(
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MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
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Register SrcReg = TRI->getMatchingSuperReg(
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MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
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BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
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.addImm(0);
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MBBI->eraseFromParent(); // The pseudo instruction is gone now.
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return true;
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}
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// This function expands the PseudoRV32ZdinxSD for storing a double-precision
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// floating-point value into memory by generating an equivalent instruction
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// sequence for RV32.
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bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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DebugLoc DL = MBBI->getDebugLoc();
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const TargetRegisterInfo *TRI = STI->getRegisterInfo();
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Register Lo =
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TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
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Register Hi =
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TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
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if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
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Hi = RISCV::X0;
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auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
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.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
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.addReg(MBBI->getOperand(1).getReg())
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.add(MBBI->getOperand(2));
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MachineInstrBuilder MIBHi;
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if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
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assert(MBBI->getOperand(2).getOffset() % 8 == 0);
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MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
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MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
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.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
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.add(MBBI->getOperand(1))
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.add(MBBI->getOperand(2));
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} else {
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assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
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MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
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.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
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.add(MBBI->getOperand(1))
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.addImm(MBBI->getOperand(2).getImm() + 4);
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}
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MachineFunction *MF = MBB.getParent();
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SmallVector<MachineMemOperand *> NewLoMMOs;
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SmallVector<MachineMemOperand *> NewHiMMOs;
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for (const MachineMemOperand *MMO : MBBI->memoperands()) {
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NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
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NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
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}
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MIBLo.setMemRefs(NewLoMMOs);
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MIBHi.setMemRefs(NewHiMMOs);
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MBBI->eraseFromParent();
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return true;
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}
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// This function expands PseudoRV32ZdinxLoad for loading a double-precision
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// floating-point value from memory into an equivalent instruction sequence for
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// RV32.
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bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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DebugLoc DL = MBBI->getDebugLoc();
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const TargetRegisterInfo *TRI = STI->getRegisterInfo();
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Register Lo =
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TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
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Register Hi =
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TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
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assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
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MachineInstrBuilder MIBLo, MIBHi;
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// If the register of operand 1 is equal to the Lo register, then swap the
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// order of loading the Lo and Hi statements.
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bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
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// Order: Lo, Hi
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if (!IsOp1EqualToLo) {
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MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
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.addReg(MBBI->getOperand(1).getReg())
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.add(MBBI->getOperand(2));
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}
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if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
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auto Offset = MBBI->getOperand(2).getOffset();
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assert(Offset % 8 == 0);
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MBBI->getOperand(2).setOffset(Offset + 4);
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MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
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.addReg(MBBI->getOperand(1).getReg())
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.add(MBBI->getOperand(2));
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MBBI->getOperand(2).setOffset(Offset);
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} else {
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assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
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MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
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.addReg(MBBI->getOperand(1).getReg())
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.addImm(MBBI->getOperand(2).getImm() + 4);
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}
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// Order: Hi, Lo
|
|
if (IsOp1EqualToLo) {
|
|
MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
|
|
.addReg(MBBI->getOperand(1).getReg())
|
|
.add(MBBI->getOperand(2));
|
|
}
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
SmallVector<MachineMemOperand *> NewLoMMOs;
|
|
SmallVector<MachineMemOperand *> NewHiMMOs;
|
|
for (const MachineMemOperand *MMO : MBBI->memoperands()) {
|
|
NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
|
|
NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
|
|
}
|
|
MIBLo.setMemRefs(NewLoMMOs);
|
|
MIBHi.setMemRefs(NewHiMMOs);
|
|
|
|
MBBI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
|
|
DebugLoc DL = MBBI->getDebugLoc();
|
|
Register Dst = MBBI->getOperand(0).getReg();
|
|
unsigned Mul = MBBI->getOperand(1).getImm();
|
|
RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
|
|
unsigned VTypeImm = RISCVVType::encodeVTYPE(
|
|
VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
|
|
.addReg(Dst, RegState::Define)
|
|
.addReg(RISCV::X0, RegState::Kill)
|
|
.addImm(VTypeImm);
|
|
|
|
MBBI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
class RISCVPreRAExpandPseudo : public MachineFunctionPass {
|
|
public:
|
|
const RISCVSubtarget *STI;
|
|
const RISCVInstrInfo *TII;
|
|
static char ID;
|
|
|
|
RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
|
AU.setPreservesCFG();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
StringRef getPassName() const override {
|
|
return RISCV_PRERA_EXPAND_PSEUDO_NAME;
|
|
}
|
|
|
|
private:
|
|
bool expandMBB(MachineBasicBlock &MBB);
|
|
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandAuipcInstPair(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI,
|
|
unsigned FlagsHi, unsigned SecondOpcode);
|
|
bool expandLoadLocalAddress(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
|
|
#ifndef NDEBUG
|
|
unsigned getInstSizeInBytes(const MachineFunction &MF) const {
|
|
unsigned Size = 0;
|
|
for (auto &MBB : MF)
|
|
for (auto &MI : MBB)
|
|
Size += TII->getInstSizeInBytes(MI);
|
|
return Size;
|
|
}
|
|
#endif
|
|
};
|
|
|
|
char RISCVPreRAExpandPseudo::ID = 0;
|
|
|
|
bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
|
|
STI = &MF.getSubtarget<RISCVSubtarget>();
|
|
TII = STI->getInstrInfo();
|
|
|
|
#ifndef NDEBUG
|
|
const unsigned OldSize = getInstSizeInBytes(MF);
|
|
#endif
|
|
|
|
bool Modified = false;
|
|
for (auto &MBB : MF)
|
|
Modified |= expandMBB(MBB);
|
|
|
|
#ifndef NDEBUG
|
|
const unsigned NewSize = getInstSizeInBytes(MF);
|
|
assert(OldSize >= NewSize);
|
|
#endif
|
|
return Modified;
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
while (MBBI != E) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
Modified |= expandMI(MBB, MBBI, NMBBI);
|
|
MBBI = NMBBI;
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
|
|
switch (MBBI->getOpcode()) {
|
|
case RISCV::PseudoLLA:
|
|
return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
|
|
case RISCV::PseudoLGA:
|
|
return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
|
|
case RISCV::PseudoLA_TLS_IE:
|
|
return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
|
|
case RISCV::PseudoLA_TLS_GD:
|
|
return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
|
|
case RISCV::PseudoLA_TLSDESC:
|
|
return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
|
|
unsigned SecondOpcode) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
Register ScratchReg =
|
|
MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
|
|
|
|
MachineOperand &Symbol = MI.getOperand(1);
|
|
Symbol.setTargetFlags(FlagsHi);
|
|
MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
|
|
|
|
MachineInstr *MIAUIPC =
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
|
|
MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
|
|
|
|
MachineInstr *SecondMI =
|
|
BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
|
|
.addReg(ScratchReg)
|
|
.addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
|
|
|
|
if (MI.hasOneMemOperand())
|
|
SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
|
|
RISCV::ADDI);
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
|
|
SecondOpcode);
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
|
|
SecondOpcode);
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
|
|
RISCV::ADDI);
|
|
}
|
|
|
|
bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
|
|
unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
|
|
|
|
Register FinalReg = MI.getOperand(0).getReg();
|
|
Register DestReg =
|
|
MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
|
|
Register ScratchReg =
|
|
MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
|
|
|
|
MachineOperand &Symbol = MI.getOperand(1);
|
|
Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
|
|
MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
|
|
|
|
MachineInstr *MIAUIPC =
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
|
|
MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
|
|
.addReg(ScratchReg)
|
|
.addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
|
|
.addReg(ScratchReg)
|
|
.addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
|
|
.addReg(DestReg)
|
|
.addImm(0)
|
|
.addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
|
|
.addReg(RISCV::X10)
|
|
.addReg(RISCV::X4);
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
} // end of anonymous namespace
|
|
|
|
INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
|
|
RISCV_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
|
|
RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
namespace llvm {
|
|
|
|
FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
|
|
FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
|
|
|
|
} // end of namespace llvm
|