d8e44a9ab2
This patch is an alternative to PRs #117060, #131684, #131728. The patch adds a late optimization pass that replaces conditional branches that can be statically evaluated with an unconditinal branch. Adding Michael as a co-author as most of the code that evaluates the condition comes from #131684. Co-authored-by: Michael Maitland michaeltmaitland@gmail.com
112 lines
3.3 KiB
C++
112 lines
3.3 KiB
C++
//===-- RISCVLateBranchOpt.cpp - Late Stage Branch Optimization -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file provides RISC-V specific target optimizations, currently it's
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/// limited to convert conditional branches into unconditional branches when
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/// the condition can be statically evaluated.
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///
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "RISCVSubtarget.h"
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using namespace llvm;
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#define RISCV_LATE_BRANCH_OPT_NAME "RISC-V Late Branch Optimisation Pass"
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namespace {
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struct RISCVLateBranchOpt : public MachineFunctionPass {
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static char ID;
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RISCVLateBranchOpt() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return RISCV_LATE_BRANCH_OPT_NAME; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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private:
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bool runOnBasicBlock(MachineBasicBlock &MBB) const;
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const RISCVInstrInfo *RII = nullptr;
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};
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} // namespace
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char RISCVLateBranchOpt::ID = 0;
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INITIALIZE_PASS(RISCVLateBranchOpt, "riscv-late-branch-opt",
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RISCV_LATE_BRANCH_OPT_NAME, false, false)
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bool RISCVLateBranchOpt::runOnBasicBlock(MachineBasicBlock &MBB) const {
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MachineBasicBlock *TBB, *FBB;
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SmallVector<MachineOperand, 4> Cond;
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if (RII->analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false))
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return false;
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if (!TBB || Cond.size() != 3)
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return false;
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RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm());
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assert(CC != RISCVCC::COND_INVALID);
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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// Try and convert a conditional branch that can be evaluated statically
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// into an unconditional branch.
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int64_t C0, C1;
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if (!RISCVInstrInfo::isFromLoadImm(MRI, Cond[1], C0) ||
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!RISCVInstrInfo::isFromLoadImm(MRI, Cond[2], C1))
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return false;
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MachineBasicBlock *Folded =
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RISCVInstrInfo::evaluateCondBranch(CC, C0, C1) ? TBB : FBB;
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// At this point, its legal to optimize.
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RII->removeBranch(MBB);
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// Only need to insert a branch if we're not falling through.
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if (Folded) {
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DebugLoc DL = MBB.findBranchDebugLoc();
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RII->insertBranch(MBB, Folded, nullptr, {}, DL);
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}
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// Update the successors. Remove them all and add back the correct one.
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while (!MBB.succ_empty())
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MBB.removeSuccessor(MBB.succ_end() - 1);
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// If it's a fallthrough, we need to figure out where MBB is going.
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if (!Folded) {
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MachineFunction::iterator Fallthrough = ++MBB.getIterator();
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if (Fallthrough != MBB.getParent()->end())
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MBB.addSuccessor(&*Fallthrough);
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} else
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MBB.addSuccessor(Folded);
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return true;
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}
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bool RISCVLateBranchOpt::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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auto &ST = Fn.getSubtarget<RISCVSubtarget>();
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RII = ST.getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : Fn)
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Changed |= runOnBasicBlock(MBB);
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return Changed;
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}
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FunctionPass *llvm::createRISCVLateBranchOptPass() {
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return new RISCVLateBranchOpt();
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}
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