llvm-project/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
Sam Elliott c60db55568
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
This commit moves RISC-V to auto-generate its target-specific SDNode
types. The biggest change is that SDNodes can now be validated against
their expected type profiles, and that we don't need to edit several
different files when declaring a new one.

This takes Sergei's work in #119709 and "finishes" it - by moving the
final five RISCVISD opcodes into tablegen (including defining their
types), and by ensuring the tablegen has expected closing scope
comments.

Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
2025-05-09 12:36:59 -07:00

20 lines
650 B
C++

//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "RISCVSelectionDAGInfo.h"
#define GET_SDNODE_DESC
#include "RISCVGenSDNodeInfo.inc"
using namespace llvm;
RISCVSelectionDAGInfo::RISCVSelectionDAGInfo()
: SelectionDAGGenTargetInfo(RISCVGenSDNodeInfo) {}
RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default;