295cdd5c3d
This changs the way the assembly matcher works for Aarch32 parsing. Previously there was a pile of hacks which dictated whether the CC, CCOut, and VCC operands should be present which de-facto chose if the wide/narrow (or thumb1/thumb2/arm) instruction version were chosen. This meant much of the TableGen machinery present for the assembly matching was effectively being bypassed and worked around. This patch makes the CC and CCOut operands optional which allows the ASM matcher operate as it was designed and means we can avoid doing some of the hacks done previously. This also adds the option for the target to allow the prioritizing the smaller instruction encodings as is required for Aarch32.
23 lines
923 B
ArmAsm
23 lines
923 B
ArmAsm
@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2>&1 | FileCheck %s
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@------------------------------------------------------------------------------
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@ Branch targets destined for ARM mode must == 0 (mod 4), otherwise (mod 2).
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@------------------------------------------------------------------------------
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b #2
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bl #2
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beq #2
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: b #2
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@ CHECK: note: invalid operand for instruction
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@ CHECK: note: instruction requires: thumb
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: bl #2
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@ CHECK: note: instruction requires: thumb
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@ CHECK: note: invalid operand for instruction
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: beq #2
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@ CHECK: note: invalid operand for instruction
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@ CHECK: note: instruction requires: thumb
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