Shilei Tian 72bb0a9a9c

[AMDGPU] Fix test failures when expensive checks are enabled (#130644) ...

This PR fixes test failures introduced in #127353 when expensive checks
are enabled.

For `llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll` and
`llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll`, `s59`
is no longer in live-ins because it is caller saved. Switch to `s55` in
this PR.

2025-03-11 00:35:18 -04:00

..

AArch64

[DAG] fold AVGFLOORS to AVGFLOORU for non-negative operand (#84746) (#129678)

2025-03-10 13:01:08 +00:00

AMDGPU

[AMDGPU] Fix test failures when expensive checks are enabled (#130644)

2025-03-11 00:35:18 -04:00

ARC

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ARM

Revert "[ARM][Thumb] Save FPSCR + FPEXC for save-vfp attribute"

2025-03-10 10:11:23 -05:00

AVR

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BPF

[BPF] Add load-acquire and store-release instructions under -mcpu=v4 (#108636)

2025-03-04 09:19:39 -08:00

CSKY

[CSKY] Update fp16-promote.ll test (NFC)

2025-03-05 12:42:32 +01:00

DirectX

[DirectX] Match DXC when storing RWBuffer<float> (#129911)

2025-03-06 13:18:06 -08:00

Generic

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Hexagon

[HEXAGON] Fix hvx-isel for extract_subvector op (#129672)

2025-03-06 17:02:10 -06:00

Inputs

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Lanai

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LoongArch

[LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864)

2025-03-06 16:17:12 +08:00

M68k

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Mips

[Mips] Reserve hardware register HWR2 (#127775)

2025-02-20 20:53:30 +08:00

MIR

[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)

2025-03-08 09:28:20 -05:00

MLRegAlloc

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MSP430

[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)

2025-02-25 20:32:24 +05:30

NVPTX

[NVPTX] Add intrinsics for st.bulk instruction (#128856)

2025-03-11 09:27:21 +05:30

PowerPC

[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)

2025-03-06 09:28:44 -08:00

RISCV

[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)

2025-03-10 16:20:14 -07:00

SPARC

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

SPIRV

[SPIR-V] Add SPV_INTEL_memory_access_aliasing extension (#129800)

2025-03-06 19:44:21 +01:00

SystemZ

[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509)

2025-03-04 11:49:09 +05:30

Thumb

[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)

2025-03-03 11:06:15 +05:30

Thumb2

[CodeGen] Combine two loops in SlotIndexes.cpp file (#127631)

2025-03-07 08:17:23 +07:00

VE

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

WebAssembly

[WebAssembly] Remove wasm-specific findWasmUnwindDestinations (#130374)

2025-03-10 20:56:38 -07:00

WinCFGuard

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WinEH

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X86

[X86] combineConcatVectorOps - convert X86ISD::VPERMV3 concatenation to use combineConcatVectorOps recursion

2025-03-10 18:52:59 +00:00

XCore

Revert "[MC] output inlined-at debug info (#106230)"

2025-03-07 09:45:15 +01:00

Xtensa

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