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llvm-project/llvm/test/CodeGen/RISCV
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Philip Reames fa315eceb7
[RISCV] Convert vsub.vx to vadd.vi if possible (#130669) 
We'd already had this transform for the intrinsics, but hadn't added it
for either fixed length or scalable vectors coming from normal IR.

For the record, the fact we have three different sets of patterns here
really is quite ugly.
2025-03-10 16:20:14 -07:00
..
GlobalISel
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
intrinsics
…
rvv
[RISCV] Convert vsub.vx to vadd.vi if possible (#130669)
2025-03-10 16:20:14 -07:00
abds-neg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
abds.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
abdu-neg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
abdu.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
add_sext_shl_constant.ll
[RISCV] Added test case for PR119527. NFC (#121816)
2025-01-07 13:33:22 -03:00
add_shl_constant.ll
[RISCV] Don't commute with shift if it would break sh{1,2,3}add pattern (#119527)
2025-01-06 19:23:21 +08:00
add-before-shl.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
add-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
addc-adde-sube-subc.ll
…
addcarry.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
addimm-mulimm.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
addrspacecast.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
aext-to-sext.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
aext.ll
…
align-loops.ll
…
align.ll
…
alloca.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
allow-check.ll
[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
2024-03-31 22:19:33 -07:00
alu8.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
alu16.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
alu32.ll
…
alu64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
analyze-branch.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
and-add-lsr.ll
[DAG] Avoid a crash when checking size of scalable type in visitANDLike
2024-02-05 14:30:10 -08:00
and-shl.ll
[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)
2024-12-12 07:58:36 +01:00
and.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
atomic-rmw-discard.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomic-rmw-sub.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
atomic-rmw.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomic-signext.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomicrmw-cond-sub-clamp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
atomicrmw-uinc-udec-wrap.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes.ll
[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)
2025-03-06 12:01:53 +05:30
avgceils.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
avgceilu.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
avgfloors.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
avgflooru.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bf16-promote.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-arith.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bfloat-br-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bfloat-convert.ll
[RISCV][LibCall] Add libcall for i64 -> bf16 (#130024)
2025-03-07 09:23:50 +08:00
bfloat-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bfloat-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
bitextract-mac.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bitreverse-shift.ll
[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)
2024-05-06 11:13:05 +01:00
bittest.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
blockaddress.ll
…
branch_zero.ll
…
branch-on-zero.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
branch-opt.ll
…
branch-opt.mir
[RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938)
2024-02-15 16:34:40 -08:00
branch-relaxation-rv32.ll
[RISCV][NFC] Split branch-relaxation test
2024-11-12 09:35:16 -08:00
branch-relaxation-rv64.ll
[RISCV][NFC] Split branch-relaxation test
2024-11-12 09:35:16 -08:00
branch.ll
…
bswap-bitreverse.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
bswap-shift.ll
[RISCV] Remove the TODO for folding bswap and shift from the test. (NFC) (#129972)
2025-03-06 13:02:17 +08:00
byval.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
callee-saved-fpr32s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-fpr64s.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
callee-saved-gprs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32d.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-ilp32f-ilp32d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calling-conv-lp64-lp64f-lp64d-common.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-lp64e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-rv32f-ilp32e.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
calling-conv-sext-zext.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calling-conv-vector-float.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-vector-on-stack.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
cm_mvas_mvsa.mir
[RISCV] Add scheduling info for Zcmp (#82719)
2024-02-23 15:44:57 -08:00
cmov-branch-opt.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
compress-double.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
compress-float.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
compress-inline-asm.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
compress-opt-branch.ll
[RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize.
2024-04-05 12:39:39 -07:00
compress-opt-select.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
compress.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
condbinops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
condops.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Rename some Feature* to Tune* (#117966)
2024-11-28 15:01:49 +08:00
copy-frameindex.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copyprop.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copysign-casts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ctlz-cttz-ctpop.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ctz_zero_return_test.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
debug-line.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
div-by-constant.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
div-pow2.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
div.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double_reduct.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-arith-strict.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-arith.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-br-fcmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-calling-conv.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-convert-strict.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
double-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-fcmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-frem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
double-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
double-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
double-isnan.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-maximum-minimum.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-previous-failure.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
double-round-conv-sat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
double-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-select-icmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-stack-spill-restore.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
double-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
dso_local_equivalent.ll
…
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
eh-dwarf-cfa.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
elf-preemption.ll
…
emutls.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
exception-pointer-register.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
fastcc-bf16.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-float.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-half.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fastcc-int.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-without-f-reg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
features-info.ll
[RISCV] Tune flag for fast vrgather.vv (#124664)
2025-03-03 16:04:49 -08:00
fixed-csr.ll
[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)
2024-12-06 14:07:27 -05:00
fixups-diff.ll
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
2024-04-26 08:30:27 -07:00
fli-licm.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
float-arith-strict.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-arith.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-bit-preserving-dagcombines.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-br-fcmp.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
float-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-fcmp.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-frem.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-imm.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-intrinsics-strict.ll
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
2024-11-27 10:24:34 -08:00
float-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
float-isnan.ll
…
float-maximum-minimum.ll
[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)
2024-11-09 10:02:06 +00:00
float-mem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-round-conv-sat.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
float-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
float-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
float-select-icmp.ll
…
float-select-verify.ll
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
float-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
flt-rounds.ll
…
fmax-fmin.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
fold-addi-loadstore.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
fold-mem-offset.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
forced-atomics.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp16-promote.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
fp128.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fp-fcanonicalize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpclamptosat.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
fpenv.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
frame-info.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
frame.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
frameaddr-returnaddr.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
ghccc-nest.ll
…
ghccc-rv32.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
ghccc-rv64.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
ghccc-without-f-reg.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
global-merge-minsize-smalldata-nonzero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize-smalldata-zero.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-minsize.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge-offset.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
global-merge.ll
[RISCV] Enable merging of external globals by default (#117880)
2024-12-11 16:06:49 +00:00
graalcc.ll
[IR] Add GraalVM calling conventions
2023-11-17 16:30:09 +00:00
half-arith-strict.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-arith.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-bitmanip-dagcombines.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-br-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-convert-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-fcmp-strict.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-fcmp.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-frem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
half-imm.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
half-intrinsics.ll
[RISCV] Remove the TODO for fmaximum/fminimum from the tests. (NFC) (#129969)
2025-03-06 13:01:58 +08:00
half-isnan.ll
…
half-maximum-minimum.ll
…
half-mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-round-conv-sat.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
half-round-conv.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
half-select-fcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
half-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-zfa-fli.ll
…
half-zfa.ll
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
hoist-global-addr-base.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
hwasan-check-memaccess.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
i32-icmp.ll
…
i64-icmp.ll
…
iabs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
idiv_large.ll
…
imm-cse.ll
…
imm.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
indirectbr.ll
…
init-array.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
inline-asm-abi-names.ll
[RISCV] Remove gp and tp from callee saved register lists. (#76483)
2023-12-27 21:36:03 -08:00
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-d-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-f-modifier-N.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-mem-constraint-2.ll
[test][RISCV] Precommit inline asm tests for #104925
2024-08-26 13:30:23 +03:00
inline-asm-mem-constraint.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
inline-asm-s-constraint-error.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-s-constraint.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-v-constraint.ll
[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283)
2024-12-06 00:48:05 +08:00
inline-asm-xsfvcp.ll
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
inline-asm-zdinx-constraint-r.ll
[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)
2024-10-18 18:17:23 -07:00
inline-asm-zfh-constraint-f.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
inline-asm-zfh-modifier-N.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-zfinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm-zhinx-constraint-r.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
inline-option-directive.ll
…
instruction-count-remark.mir
[CodeGen] Fix InstructionCount remarks for MI bundles (#107621)
2024-10-02 13:37:25 -07:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
intrinsic-cttz-elts-vscale.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
intrinsic-cttz-elts.ll
[RISCV] Provide a more efficient lowering for experimental.cttz.elts. (#88552)
2024-04-15 18:38:54 -07:00
ipra.ll
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
isel-optnone.ll
…
jumptable-swguarded.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
jumptable.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
kcfi-isel-mir.ll
[RISCV] Add call preserved regmask to tail calls. (#122181)
2025-01-08 16:19:31 -08:00
kcfi-mir.ll
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
kcfi-patchable-function-prefix.ll
…
kcfi.ll
…
lack-of-signed-truncation-check.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
large-stack.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
legalize-fneg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
libcall-tail-calls.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
lit.local.cfg
…
live-sp.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
llvm.exp10.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
llvm.frexp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
load-setcc-combine.ll
[DAGCombiner] Allow tryToFoldExtOfLoad to use a sextload for zext nneg. (#81714)
2024-02-17 11:37:13 -08:00
load-store-pair.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
local-stack-slot-allocation.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
loop-strength-reduce-add-cheaper-than-mul.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
loop-strength-reduce-loop-invar.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
lpad.ll
[RISCV] Remove Last Traces of User Interrupts (#129300)
2025-03-04 11:36:16 -08:00
lsr-legaladdimm.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
machine-combiner.mir
…
machine-copyprop-noop-removal.mir
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
machine-cp.mir
Revert "[MCP] Enhance MCP copy Instruction removal for special case (#70778)"
2023-11-27 19:39:40 +01:00
machine-cse.ll
…
machine-outliner-and-machine-copy-propagation.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
machine-outliner-call-x5-liveout.mir
[RISCV] [MachineOutliner] Analyze all candidates (#127659)
2025-02-21 12:53:13 +05:30
machine-outliner-call.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-cfi.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-leaf-descendants.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-patchable.ll
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-position.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machine-outliner-throw.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
machine-pipeliner.ll
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
machine-sink-load-immediate.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
machinelicm-address-pseudos.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
machinelicm-constant-phys-reg.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)
2024-09-11 09:53:11 -07:00
machineoutliner-x5.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
machineoutliner.mir
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
2024-11-26 23:39:45 +08:00
MachineSink-implicit-x0.mir
[CodeGen][NewPM] Port MachineSink to NPM (#115434)
2025-03-03 15:49:37 +05:30
macro-fusion-lui-addi.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
macro-fusions.mir
[RISCV] Fix macro-fusions.mir
2023-12-22 14:49:59 +08:00
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
make-compressible-zbc-zhinx.mir
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
make-compressible-zbc.mir
[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC
2024-09-16 12:51:07 -07:00
make-compressible-zfinx.mir
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
make-compressible.mir
[RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (#81844)
2024-02-22 15:51:19 +08:00
mem64.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
mem.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp-optsize.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memcpy-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memcpy.ll
Reapply "[RISCV] Rework memcpy test (#120364)"
2025-01-13 12:06:26 +08:00
memmove.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
memset-inline.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
memset-pattern.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
min-max.ll
…
mir-target-flags.ll
[RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)
2024-01-07 12:43:39 -08:00
misched-load-clustering.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
misched-mem-clustering.mir
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
misched-postra-direction.mir
Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)
2025-02-12 18:54:39 +05:30
miss-sp-restore-eh.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
…
mul.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
musttail-call.ll
…
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
narrow-shl-cst.ll
…
neg-abs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
nest-register.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
nomerge.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
nontemporal-scalable.ll
…
nontemporal.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
O0-pipeline.ll
[RISCV] Move VMV0 elimination past machine SSA opts (#126850)
2025-02-20 12:41:05 +08:00
O3-pipeline.ll
[RISCV] Generate MIPS load/store pair instructions (#124717)
2025-03-07 09:21:36 +01:00
opt-w-instrs.mir
[RISCV] Add PseudoCCMOVGPRNoX0 test caes for RISCVOptWInstrs. NFC
2025-01-31 15:19:44 -08:00
option-nopic.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
option-relax-relocation.ll
[RISCV] Force relocations if initial MCSubtargetInfo contains FeatureRelax (#77436)
2024-01-09 11:24:21 -08:00
option-relax.ll
…
option-rvc.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
orc-b-patterns.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
out-of-reach-emergency-slot.mir
[RISCV] fix SP recovery in a function epilogue (#110809)
2024-10-04 12:22:11 +03:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
patchable-function-entry.ll
[MC] Parse SHF_LINK_ORDER argument before section group name (#77407)
2024-01-09 10:42:34 -08:00
pei-crash.ll
[RISCV] Fix crash in PEI with empty entry block with Zcmp (#72117)
2023-11-17 16:18:44 +01:00
pic-models.ll
…
postra-copy-expand.mir
[RISCV] Attach an implicit source operand on vector copies (#126155)
2025-02-08 16:25:27 -08:00
pr40333.ll
…
pr51206.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
pr56457.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
pr58025.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr58286.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr58511.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr63365.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr63816.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr64503.ll
…
pr64645.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
pr64772.ll
…
pr64935.ll
…
pr65025.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
pr66603.ll
…
pr68855.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
pr69586.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
pr80052.mir
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
2024-02-01 13:25:15 -08:00
pr84200.ll
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
2024-03-07 15:03:51 -08:00
pr84653_pr85190.ll
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
pr88365.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
pr90652.ll
[RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659)
2024-05-01 06:51:36 +08:00
pr90730.ll
[RISCV][ISel] Allow opaque constants in hasAndNotCompare (#92926)
2024-05-22 00:48:26 +08:00
pr92193.ll
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195)
2024-05-15 12:39:28 -07:00
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.
2024-07-29 17:15:02 -07:00
pr95271.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
pr95284.ll
[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)
2024-10-31 16:40:29 +00:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)
2024-09-27 13:48:01 -07:00
prefer-w-inst.ll
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefer-w-inst.mir
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefetch.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
prolog-epilogue.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
push-pop-opt-crash.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
push-pop-popret.ll
[RISCV] Remove Last Traces of User Interrupts (#129300)
2025-03-04 11:36:16 -08:00
qci-interrupt-attr-fpr.ll
[RISCV] QCI Interrupt Support (#129957)
2025-03-06 13:31:08 -08:00
qci-interrupt-attr.ll
[RISCV] QCI Interrupt Support (#129957)
2025-03-06 13:31:08 -08:00
rda-stack.mir
[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)
2025-02-04 10:04:19 -05:00
readcyclecounter.ll
…
readsteadycounter.ll
[RISCV] Support llvm.readsteadycounter intrinsic
2024-02-21 13:12:14 +08:00
reduce-unnecessary-extension.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
reduction-formation.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
redundant-copy-from-tail-duplicate.ll
[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)
2024-09-10 18:47:20 -07:00
regalloc-last-chance-recoloring-failure.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
relax-per-target-feature.ll
[RISCV] Update relax-per-target-feature.ll to use hexadecimal constants. NFC
2023-12-14 21:08:01 -08:00
rem.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
remat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
renamable-copy.mir
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
repeated-fp-divisors.ll
…
replace-with-veclib-sleef-scalable.ll
[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)
2024-11-26 12:25:54 +03:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
2024-08-15 10:37:04 +08:00
riscv-codegenprepare-asm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
riscv-codegenprepare.ll
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
riscv-func-target-feature.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
riscv-tail-dup-size.ll
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
2024-08-01 12:24:25 +08:00
rotl-rotr.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32-fuchsia.ll
…
rv32-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32e.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
rv32i-rv64i-float-double.ll
[RISCV] Remove the TODO for lowering f32 libcall on RV64 with lp64 abi. (NFC)
2025-03-07 10:52:04 +08:00
rv32i-rv64i-half.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv32xtheadba.ll
[RISCV] Fix XTheadba patterns broken since cfc574a6cd13d2d0b77110b579c5cfcec744129f.
2024-12-26 21:50:35 -08:00
rv32xtheadbb.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv32xtheadbs.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
rv32zba.ll
[RISCV] Zba testing improvements. NFC
2024-11-14 13:47:49 -08:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv32zbb.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv32zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-double-convert-strict.ll
[RISCV] Add test cases for RV64 i128<->half/float/double (#115124)
2024-11-06 11:36:30 -08:00
rv64-double-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-float-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-float-convert.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-half-convert-strict.ll
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
2024-12-02 09:06:08 -08:00
rv64-half-convert.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-inline-asm-pairs.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-large-stack.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64-patchpoint.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
rv64-stackmap-args.ll
[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)
2024-12-11 17:41:19 +08:00
rv64-stackmap-frame-setup.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-stackmap-nops.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
rv64-stackmap.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-statepoint-call-lowering-x1.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering-x2.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-statepoint-call-lowering.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
rv64-trampoline.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64-typepromotion.ll
[RISCV][TypePromotion] Dont generate truncs if PromotedType is greater than Source Type (#86941)
2024-03-28 21:22:05 -07:00
rv64d-double-convert-strict.ll
[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
2024-11-05 21:48:38 -08:00
rv64d-double-convert.ll
[RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC
2024-11-05 21:12:09 -08:00
rv64e.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
rv64f-float-convert-strict.ll
[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC
2024-11-05 21:48:38 -08:00
rv64f-float-convert.ll
…
rv64i-complex-float.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-demanded-bits.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64i-double-softfloat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64i-single-softfloat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
rv64xtheadba.ll
[RISCV] Use add_like_non_imm12 in XTheadba patterns to match Zba.
2024-12-29 12:39:37 -08:00
rv64xtheadbb.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64xtheadbs.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
rv64zba.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64zbb-intrinsic.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64zbb-zbkb.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64zbb.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV][DAGCombine] Combine sext_inreg (shl X, Y), i32 into sllw X, Y (#111101)
2024-10-04 16:03:09 +08:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.
2024-08-14 15:18:10 -07:00
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-convert.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat_plus.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
sadd_sat.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
saverestore-scs.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
saverestore.ll
…
scmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)
2024-08-23 14:06:12 +01:00
sdiv-pow2-cmov.ll
[RISCV][SDAG] Prefer ShortForwardBranch to lower sdiv by pow2 (#67364)
2023-11-10 21:38:47 +08:00
select-and.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-bare.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-binop-identity.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
select-cc.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-const.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
select-constant-xor.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-optimize-multiple.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
select-to-and-zext.ll
…
select.ll
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
2025-02-25 10:04:57 -08:00
selectcc-to-shiftand.ll
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)
2024-08-06 20:27:14 -07:00
setcc-logic.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
sext-zext-trunc.ll
[DAGCombiner][RISCV] CSE zext nneg and sext. (#82597)
2024-02-22 09:06:49 -08:00
sextw-removal-debug.mir
[RISCV] Ignore debug instructions in hasAllNBitUsers in RISCVOptWInstrs.
2023-12-03 21:27:50 -08:00
sextw-removal.ll
[MachineCopyPropagation] Recognise and delete no-op moves produced after forwarded uses (#129889)
2025-03-10 13:22:59 +00:00
shadowcallstack.ll
[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)
2024-11-08 00:16:45 +08:00
shift-amount-mod.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shift-and.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
shift-masked-shamt.ll
…
shifts.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shl-cttz.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
shl-demanded.ll
…
shlimm-addimm.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
short-forward-branch-opt.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
shrinkwrap-jump-table.ll
[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables
2025-01-31 14:05:34 -08:00
shrinkwrap.ll
[RISCV] Add shrinkwrap test cases showing gaps in current impl
2024-11-27 11:14:51 -08:00
sifive7-enable-intervals.mir
[MISched] Unify the way to specify scheduling direction (#119518)
2024-12-12 11:24:07 +08:00
signbit-test.ll
[RISCV] Enable the TypePromotion pass from AArch64/ARM.
2024-02-13 09:57:48 -08:00
signed-truncation-check.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
[RISCV] Use BuildPairF64 and SplitF64 for bitcast i64<->f64 on rv32 regardless of Zfa. (#85982)
2024-03-21 08:52:51 -07:00
spill-fpr-scalar.ll
[RISCV] Rewrite spill-fpr-scalar.ll test to not use vsetvli. NFC (#91428)
2024-05-08 11:33:05 +08:00
spir-kernel-cc.ll
…
split-offsets.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
split-sp-adjust.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
split-store.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
split-udiv-by-constant.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
split-urem-by-constant.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
srem-lkk.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
srem-seteq-illegal-types.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
srem-vector-lkk.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
srodata.ll
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
ssub_sat_plus.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
ssub_sat.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
stack-clash-prologue-nounwind.ll
[RISCV] Compute liveins for new basic blocks in emitStackProbeInline.
2024-12-10 12:37:45 -08:00
stack-clash-prologue.ll
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
stack-folding.ll
[RISCV] Remove gp and tp from callee saved register lists. (#76483)
2023-12-27 21:36:03 -08:00
stack-guard-global.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-guard-tls.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-inst-compress.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
stack-offset.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
stack-protector-target.ll
[RISCV] Use the thread local stack protector for Android targets (#87672)
2024-05-13 08:52:59 -07:00
stack-realignment-with-variable-sized-objects.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
stack-realignment.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
stack-slot-coloring.mir
[win] NFC: Rename EHCatchret to EHCont to allow for EH Continuation targets that aren't catchret instructions (#129953)
2025-03-06 09:28:44 -08:00
stack-slot-size.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stack-store-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
stores-of-loads-merging.ll
[RISCV] Added test for dag spill fix
2025-03-08 14:55:20 -03:00
subtarget-features-std-ext.ll
…
switch-width.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
tagged-globals.ll
…
tail-calls.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
target-abi-invalid.ll
…
target-abi-valid.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
thread-pointer.ll
…
tls-models.ll
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
tlsdesc-symbol.ll
[llvm][lld] Pre-commit tests for RISCV TLSDESC symbols
2024-03-20 13:39:39 -07:00
trunc-free.ll
…
trunc-nsw-nuw.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
typepromotion-overflow.ll
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
2024-11-25 18:59:31 -08:00
uadd_sat_plus.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
uadd_sat.ll
…
ucmp.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
umulo-128-legalisation-lowering.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
unaligned-load-store.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
unroll-loop-cse.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
urem-lkk.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
urem-seteq-illegal-types.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
urem-vector-lkk.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
usub_sat_plus.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
usub_sat.ll
…
vararg-ilp32e.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
vararg.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
varargs-with-fp-and-second-adj.ll
[RISCV] fix SP recovery in varargs functions (#114316)
2024-11-06 19:30:32 +03:00
vector-abi.ll
[RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)
2024-01-07 12:43:39 -08:00
vector-tuple-zeroinitializer.ll
[RISCV] Handle zeroinitializer of vector tuple Type (#113995)
2024-12-04 13:40:02 +08:00
verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
vscale-demanded-bits.ll
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
wide-scalar-shift-legalization.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
xaluo.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
xcvalu.ll
[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)
2024-10-01 11:22:02 +10:00
xcvbi.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
xcvbitmanip.ll
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem-heuristic.ll
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
2024-12-31 10:56:28 +08:00
xcvmem.ll
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
xqccmp_mvas_mvsa.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-additional-stack.ll
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-callee-saved-gprs.ll
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-push-pop-popret.ll
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xqccmp-with-float.ll
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
xray-attribute-instrumentation.ll
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
xtheadfmemidx.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
xtheadmac.ll
[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
2024-11-15 17:53:14 +08:00
xtheadmemidx.ll
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
xtheadmempair.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zbb-cmp-combine.ll
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
zbb-logic-neg-imm.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zcb-regalloc-hints.ll
[RISCV] Add regalloc hints for Zcb instructions. (#78949)
2024-01-23 09:33:06 -08:00
zcmp-additional-stack.ll
[RISCV] Allow spilling to unused Zcmp Stack (#125959)
2025-02-06 19:45:47 -08:00
zcmp-cm-popretz.mir
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
zcmp-cm-push-pop.mir
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
2025-01-28 21:03:12 +05:30
zcmp-prolog-epilog-crash.mir
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
zcmp-with-float.ll
[RISCV] Allow spilling to unused Zcmp Stack (#125959)
2025-02-06 19:45:47 -08:00
zdinx-asm-constraint.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-boundary-check.ll
Revert "[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)" and follow up commit.
2025-02-13 09:57:33 -08:00
zdinx-large-spill.mir
[RISCV][CFI] add function epilogue cfi information (#110810)
2024-11-06 00:20:21 +03:00
zdinx-memoperand.ll
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
2025-01-27 22:10:51 -08:00
zext-with-load-is-free.ll
[RISCV] Remove setJumpIsExpensive(). (#74647)
2023-12-13 09:37:25 -08:00
zfh-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfh-half-intrinsics.ll
…
zfhmin-half-intrinsics-strict.ll
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
2024-11-25 16:12:45 -08:00
zfhmin-half-intrinsics.ll
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
2024-09-01 12:15:00 -07:00
zfhmin-imm.ll
…
zicfilp-indirect-branch.ll
[RISCV] Avoid using x7/t2 for indirect branches which need landing pad. (#68292)
2024-05-02 10:32:40 +08:00
zmmul.ll
…