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llvm-project/llvm/test/CodeGen/RISCV
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Xinlong Chen b670265b58
[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461) 
ADD(X,X) is equivalent to SHL(X,1), so bit[0] is always zero.

This allows downstream folds like `and(add(x,x), 1) -> 0`.

Fixes #186091
2026-03-23 16:10:36 +00:00
..
GlobalISel
[GlobalISel] Fold a bitwiseop (~b +/- c) -> a bitwiseop ~(b -/+ c) (#181725)
2026-03-20 15:53:07 +00:00
intrinsics
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rvv
[SelectionDAG] Add CTTZ_ELTS[_ZERO_POISON] nodes. NFCI (#185600)
2026-03-16 14:39:35 +08:00
abds-neg.ll
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abds.ll
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abdu-neg.ll
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abdu.ll
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add_sext_shl_constant.ll
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add_shl_constant.ll
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add-before-shl.ll
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add-imm64-to-sub.ll
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add-imm.ll
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addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
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addrspacecast.ll
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aext-to-sext.ll
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aext.ll
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align-loops.ll
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align.ll
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alloca.ll
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allow-check.ll
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alu8.ll
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alu16.ll
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alu32.ll
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alu64.ll
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analyze-branch.ll
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and-add-lsr.ll
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and-negpow2-cmp.ll
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and-shl.ll
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and.ll
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arith-with-overflow.ll
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atomic-cmpxchg-branch-on-result.ll
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atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll
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atomic-fence.ll
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atomic-load-store.ll
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atomic-load-zext.ll
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atomic-rmw-discard.ll
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atomic-rmw-minmax.ll
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atomic-rmw-sub.ll
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atomic-rmw.ll
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atomic-signext.ll
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atomicrmw-cond-sub-clamp.ll
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atomicrmw-uinc-udec-wrap.ll
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attributes-andes.ll
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attributes-module-flag.ll
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attributes-qc.ll
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attributes-sifive.ll
[RISCV] Add Xsfmm32a shorthand extension. (#181957)
2026-02-17 21:18:52 -08:00
attributes-thead.ll
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attributes.ll
[RISCV][MC] Add support of Zvzip extension (#185614)
2026-03-11 14:22:02 +08:00
avgceils.ll
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avgceilu.ll
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avgfloors.ll
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avgflooru.ll
[TargetLowering][RISCV] Disable the special illegal type expansion of ISD::AVGFLOORU on RV32 (#181073)
2026-02-25 23:26:16 -08:00
bf16-promote.ll
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bfloat-arith.ll
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bfloat-br-fcmp.ll
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bfloat-convert-half.ll
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bfloat-convert.ll
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bfloat-fcmp.ll
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bfloat-frem.ll
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bfloat-imm.ll
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bfloat-isnan.ll
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bfloat-mem.ll
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bfloat-select-fcmp.ll
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bfloat-select-icmp.ll
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bfloat.ll
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bigendian-double-bitmanip.ll
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bigendian-f64-call.ll
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bigendian-load-store.ll
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bitextract-mac.ll
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bitreverse-shift.ll
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bittest.ll
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blockaddress.ll
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branch_zero.ll
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branch-on-zero.ll
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branch-opt.ll
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branch-opt.mir
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branch-rel.mir
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branch-relaxation-rv32.ll
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branch-relaxation-rv32e.ll
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branch-relaxation-rv64.ll
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branch.ll
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bswap-bitreverse.ll
[RISCV] Support scalar bitreverse using P extension rev instruction. (#183245)
2026-02-25 12:42:59 -08:00
bswap-shift.ll
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byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
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callee-saved-gprs.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
calleetypeid-directcall-mismatched.ll
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calling-conv-half.ll
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calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32e.ll
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calling-conv-ilp32f-ilp32d-common.ll
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calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
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calling-conv-lp64.ll
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calling-conv-lp64e.ll
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calling-conv-p-ext-vector.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
calling-conv-preserve-most.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-rv32f-ilp32e.ll
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calling-conv-sext-zext.ll
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calling-conv-vector-float.ll
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calling-conv-vector-on-stack.ll
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calls.ll
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callsite-emit-calleetypeid-tailcall.ll
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callsite-emit-calleetypeid.ll
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cfi-multiple-locations.mir
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clear-cache.ll
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clmul.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
clmulh.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
clmulr.ll
[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)
2026-02-22 19:20:16 -08:00
cm_mvas_mvsa.ll
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cm_mvas_mvsa.mir
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cmov-branch-opt.ll
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cmp-bool.ll
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codemodel-lowering.ll
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combine-clmul.ll
[DAG] visitCLMUL - fold (clmul x, c_pow2) -> (shl x, log2(c_pow2)) (#184049)
2026-03-02 10:52:51 +00:00
combine-storetomstore.ll
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compress-double.ll
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compress-float.ll
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compress-inline-asm.ll
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compress-opt-branch.ll
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compress-opt-select.ll
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compress.ll
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condbinops.ll
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condops.ll
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
2026-02-20 18:00:07 -08:00
constpool-known-bits.ll
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convert-highly-predictable-select-to-branch.ll
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copy-frameindex.mir
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copyprop.ll
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copysign-casts.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
csr-first-use-cost.ll
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ctlz-cttz-ctpop.ll
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ctz_zero_return_test.ll
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debug-line.ll
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di-assignment-tracking-vector.ll
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disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)
2026-02-25 22:54:34 +01:00
div-by-constant.ll
[LegalizeTypes] Expand UDIV/UREM by constant via chunk summation (#146238)
2026-03-19 17:58:54 +05:30
div-pow2.ll
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div.ll
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double_reduct.ll
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double-arith-strict.ll
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double-arith.ll
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double-bitmanip-dagcombines.ll
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double-br-fcmp.ll
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double-calling-conv.ll
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double-convert-strict.ll
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double-convert.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-fcmp-strict.ll
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double-fcmp.ll
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double-frem.ll
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double-imm.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-intrinsics-strict.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-intrinsics.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-isnan.ll
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double-maximum-minimum.ll
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double-mem.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
double-previous-failure.ll
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double-round-conv-sat.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-round-conv.ll
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double-select-fcmp.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-select-icmp.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
double-stack-spill-restore.ll
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
2026-03-02 20:06:10 -08:00
double-zfa.ll
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dso_local_equivalent.ll
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dwarf-eh.ll
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early-clobber-tied-def-subreg-liveness.ll
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eh-dwarf-cfa.ll
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elf-preemption.ll
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emit-x8-as-fp.ll
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emutls.ll
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exception-pointer-register.ll
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fastcc-bf16.ll
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fastcc-float.ll
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fastcc-half.ll
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fastcc-int.ll
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fastcc-without-f-reg.ll
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features-info.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
fixed-csr.ll
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fixups-diff.ll
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fli-licm.ll
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float-arith-strict.ll
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float-arith.ll
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float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
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float-convert-strict.ll
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float-convert.ll
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float-fcmp-strict.ll
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float-fcmp.ll
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float-frem.ll
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float-imm.ll
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float-intrinsics-strict.ll
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float-intrinsics.ll
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float-isnan.ll
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float-maximum-minimum.ll
[SelectionDAG] Remove NoNaNsFPMath uses (#183448)
2026-03-10 14:06:42 +08:00
float-mem.ll
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float-round-conv-sat.ll
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float-round-conv.ll
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float-select-fcmp.ll
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float-select-icmp.ll
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float-select-verify.ll
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float-zfa.ll
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flt-rounds.ll
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fma-combine.ll
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fmax-fmin.ll
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fold-addi-loadstore-zilsd.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
fold-addi-loadstore.ll
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fold-binop-into-select-return-constant.ll
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fold-binop-into-select.ll
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fold-masked-merge.ll
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fold-mem-offset-zilsd.ll
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fold-mem-offset.ll
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fold-mem-offset.mir
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forced-atomics.ll
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fp16-promote.ll
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fp128.ll
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fp-fcanonicalize.ll
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fpclamptosat.ll
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fpenv-xlen.ll
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fpenv.ll
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frame-info.ll
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frame.ll
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frameaddr-returnaddr.ll
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frm-dependency.ll
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frm-write-in-loop.ll
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get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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ghccc-nest.ll
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ghccc-rv32.ll
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ghccc-rv64.ll
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ghccc-without-f-reg.ll
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global-merge-minsize-smalldata-nonzero.ll
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global-merge-minsize-smalldata-zero.ll
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global-merge-minsize.ll
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global-merge-offset.ll
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global-merge.ll
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graalcc.ll
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half-arith-strict.ll
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half-arith.ll
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half-bitmanip-dagcombines.ll
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half-br-fcmp.ll
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half-convert-strict.ll
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half-convert.ll
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half-fcmp-strict.ll
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half-fcmp.ll
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half-frem.ll
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half-imm.ll
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half-intrinsics.ll
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half-isnan.ll
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half-maximum-minimum.ll
[SelectionDAG] Remove NoNaNsFPMath uses (#183448)
2026-03-10 14:06:42 +08:00
half-mem.ll
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half-round-conv-sat.ll
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half-round-conv.ll
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half-select-fcmp.ll
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half-select-icmp.ll
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half-zfa-fli.ll
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half-zfa.ll
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hoist-global-addr-base.ll
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hwasan-check-memaccess.ll
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i32-icmp.ll
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i64-icmp.ll
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iabs.ll
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icmp-non-byte-sized.ll
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idiv_large.ll
[DAG] Fold (X +/- Y) & Y --> ~X & Y when Y is a power of 2 (or zero). (#181677)
2026-02-18 12:19:21 +00:00
imm-cse.ll
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imm.ll
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indirectbr.ll
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init-array.ll
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inline-asm-abi-names.ll
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inline-asm-bf-constraint-f.ll
[RISCV] Support 'f' Inline Assembly Constraint for bfloat16 (#184566)
2026-03-05 20:21:22 -08:00
inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
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inline-asm-d-modifier-N.ll
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inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
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inline-asm-f-modifier-N.ll
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inline-asm-fixed-v-constraint.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm-mem-constraint-2.ll
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inline-asm-mem-constraint.ll
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inline-asm-s-constraint-error.ll
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inline-asm-s-constraint.ll
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inline-asm-v-constraint.ll
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inline-asm-xsfvcp.ll
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inline-asm-zdinx-constraint-r.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
inline-asm-zfh-constraint-f.ll
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inline-asm-zfh-modifier-N.ll
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inline-asm-zfinx-constraint-r.ll
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inline-asm-zhinx-constraint-r.ll
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inline-asm.ll
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inline-option-directive.ll
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instruction-count-remark.mir
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interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
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interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll
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interrupt-attr-ret-error.ll
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interrupt-attr.ll
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ipra.ll
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isel-optnone.ll
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jumptable-swguarded.ll
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jumptable.ll
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kcfi-isel-mir.ll
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kcfi-mir.ll
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kcfi-patchable-function-prefix.ll
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kcfi.ll
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lack-of-signed-truncation-check.ll
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large-codemodel-sections.ll
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
large-stack.ll
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legalize-fneg.ll
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libcall-tail-calls.ll
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lit.local.cfg
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live-sp.mir
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llvm.exp10.ll
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llvm.frexp.ll
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load-narrow-shift-mask-combine.ll
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load-setcc-combine.ll
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load-store-pair.ll
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local-stack-slot-allocation.ll
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loop-strength-reduce-add-cheaper-than-mul.ll
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loop-strength-reduce-loop-invar.ll
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lpad.ll
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lrint-conv.ll
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lsr-legaladdimm.ll
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machine-combiner-mir.ll
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machine-combiner-strategies.ll
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machine-combiner.ll
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machine-combiner.mir
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machine-copyprop-noop-removal.mir
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machine-copyprop-simplifyinstruction.mir
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machine-cp.mir
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machine-cse.ll
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machine-outliner-and-machine-copy-propagation.ll
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machine-outliner-call-reg-live-across.mir
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machine-outliner-call-x5-liveout.mir
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machine-outliner-call.ll
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machine-outliner-cfi.mir
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machine-outliner-leaf-descendants.ll
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machine-outliner-lpad.ll
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machine-outliner-patchable.ll
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machine-outliner-position.mir
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machine-outliner-throw.ll
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machine-pipeliner.ll
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machine-sink-load-immediate.ll
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machinelicm-address-pseudos.ll
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
machinelicm-constant-phys-reg.ll
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machineoutliner-jumptable.mir
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machineoutliner-pcrel-lo.mir
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machineoutliner-x5.mir
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machineoutliner.mir
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MachineSink-implicit-x0.mir
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macho-relocs.ll
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macro-fusion-add-mem.mir
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macro-fusion-logic-imm-reg.mir
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macro-fusion-logic-reg-imm.mir
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macro-fusion-logic-reg-reg.mir
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macro-fusion-lui-addi.ll
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
macro-fusion-mul-add.mir
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macro-fusion-shift-bit-extract.mir
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macro-fusions.mir
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
make-compressible-for-store-address.mir
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make-compressible-rv64.mir
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make-compressible-xqci.mir
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make-compressible-zbc-zhinx.mir
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make-compressible-zbc.mir
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make-compressible-zfinx.mir
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make-compressible-zilsd.mir
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make-compressible.mir
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mask-variable-shift.ll
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mem64.ll
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mem.ll
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memcmp-optsize.ll
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memcmp.ll
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memcpy-inline.ll
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memcpy.ll
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memmove.ll
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memset-inline.ll
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memset-pattern.ll
[LowerMemIntrinsics][AMDGPU] Optimize memset.pattern lowering (#185901)
2026-03-13 10:37:33 +01:00
min-max.ll
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mir-target-flags.ll
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misched-load-clustering.ll
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misched-mem-clustering.mir
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misched-postra-direction.mir
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misched-store-clustering.ll
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miss-sp-restore-eh.ll
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module-elf-flags.ll
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module-target-abi2.ll
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module-target-abi3.ll
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module-target-abi.ll
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mul-expand.ll
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mul.ll
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musttail-call.ll
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musttail.ll
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naked-fn-with-frame-pointer.ll
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narrow-shl-cst.ll
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neg-abs.ll
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nest-register.ll
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nomerge.ll
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nontemporal-scalable.ll
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nontemporal.ll
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note-gnu-property-zicfiss.ll
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O0-pipeline.ll
[NFC][CodeGen] Rename CallBrPrepare pass to InlineAsmPrepare (#181547)
2026-02-17 15:37:35 -08:00
O3-pipeline.ll
[CodeGenPrepare][NFC] Get BPI/BFI from pass/analysis manager (#186651)
2026-03-15 17:41:22 +01:00
opt-w-instrs-p-ext.mir
[RISCV] Add MERGE, MVM, and MVMN to isSignExtendedW in RISCVOptWInstrs. (#183433)
2026-02-25 21:26:13 -08:00
opt-w-instrs.mir
[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)
2026-03-03 12:38:00 +05:30
option-exact-inlineasm.ll
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option-nopic.ll
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option-norelax.ll
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option-norvc.ll
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option-pic.ll
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option-relax-relocation.ll
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option-relax.ll
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option-rvc.ll
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optnone-store-no-combine.ll
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or-is-add.ll
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orc-b-patterns.ll
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out-of-reach-emergency-slot.mir
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overflow-intrinsic-optimizations.ll
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overflow-intrinsics.ll
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patchable-function-entry.ll
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pei-crash.ll
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pic-models.ll
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pipeline-options.ll
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poison-legalization.ll
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postra-copy-expand.mir
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pr40333.ll
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pr51206.ll
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pr53662.mir
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pr55201.ll
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pr56110.ll
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pr56457.ll
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pr58025.ll
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pr58286.ll
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pr58511.ll
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pr63365.ll
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pr63816.ll
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pr64503.ll
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pr64645.ll
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pr64772.ll
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pr64935.ll
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pr65025.ll
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pr66603.ll
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pr68855.ll
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pr69586.ll
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pr80052.mir
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pr84200.ll
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pr84653_pr85190.ll
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pr88365.ll
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pr90652.ll
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pr90730.ll
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pr92193.ll
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pr94145.ll
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pr94265.ll
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pr95271.ll
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pr95284.ll
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pr96366.ll
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pr97304.ll
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pr101786.ll
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pr135206.ll
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pr142004.ll
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pr145360.ll
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pr145363.ll
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pr148084.ll
[RISCV][llvm] Rename zvqdotq to zvdot4a8i (#179393)
2026-02-24 04:44:07 +00:00
pr153598.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
pr158121.ll
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pr176001.ll
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pr186969.ll
[DAGCombiner] Move the XORHandle in rebuildSetCC inside the while loop. (#187189)
2026-03-18 09:30:05 -07:00
prefer-w-inst.ll
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prefer-w-inst.mir
…
prefetch.ll
[RISCV] Relax codegen predicates for HINT-based instructions (#179872)
2026-03-02 17:24:22 +08:00
print-pipeline-passes.ll
…
prolog-epilogue.ll
…
push-pop-opt-crash.ll
…
push-pop-popret.ll
…
qci-interrupt-attr-fpr.ll
…
qci-interrupt-attr.ll
…
rda-entry-bb-is-a-loop.mir
…
rda-liveins.mir
…
rda-stack.mir
…
readcyclecounter.ll
…
readsteadycounter.ll
…
reassoc-shl-addi-add.ll
…
reduce-unnecessary-extension.ll
…
reduction-formation.ll
…
redundant-copy-elim.ll
…
redundant-copy-from-tail-duplicate.ll
…
regalloc-last-chance-recoloring-failure.ll
[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)
2026-03-04 05:46:26 +00:00
relative-reloc.ll
…
relax-per-target-feature.ll
…
rem.ll
…
remat.ll
…
renamable-copy.mir
…
repeated-fp-divisors.ll
…
replace-with-veclib-sleef-scalable.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegen-prepare-atp.ll
…
riscv-codegenprepare-asm.ll
…
riscv-codegenprepare.ll
…
riscv-func-target-feature.ll
…
riscv-macho.ll
…
riscv-promote-constant.ll
…
riscv-scavenge-crash-2nd-pass-rv32.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
riscv-scavenge-crash-2nd-pass-rv64.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
riscv-tail-dup-size.ll
…
riscv-zihintpause.ll
[RISCV] Relax codegen predicates for HINT-based instructions (#179872)
2026-03-02 17:24:22 +08:00
rnmi-interrupt-attr-error.ll
…
rnmi-interrupt-attr.ll
…
rotl-rotr.ll
…
rv32-fuchsia.ll
…
rv32-inline-asm-pairs.ll
…
rv32-merge-non-arg-reg.mir
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
rv32-move-merge-crash.ll
[RISCV] Add guard to prevent GPRPair merge on targets without Zdinx or P (#186600)
2026-03-22 10:26:33 -07:00
rv32-move-merge.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32p.ll
[RISCV] Fold (WADDAU -C, -1, rs1, 0) -> (WSUBU rs1, C) where C > 0 (#186638)
2026-03-16 21:13:56 -07:00
rv32xandesperf.ll
…
rv32xtheadba.ll
…
rv32xtheadbb.ll
…
rv32xtheadbs.ll
…
rv32zba.ll
…
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
…
rv32zbb.ll
[RISCV] Select (sext_inreg (sra X, C), i8/i16) as slli+srai. (#186956)
2026-03-17 08:01:40 -07:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
…
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
…
rv32zimop-intrinsic.ll
…
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-double-convert-strict.ll
…
rv64-double-convert.ll
…
rv64-float-convert-strict.ll
…
rv64-float-convert.ll
…
rv64-half-convert-strict.ll
…
rv64-half-convert.ll
…
rv64-inline-asm-pairs.ll
…
rv64-large-stack.ll
…
rv64-patchpoint.ll
…
rv64-stackmap-args.ll
…
rv64-stackmap-fp.ll
…
rv64-stackmap-frame-setup.ll
…
rv64-stackmap-nops.ll
…
rv64-stackmap.ll
…
rv64-statepoint-call-lowering-x1.ll
…
rv64-statepoint-call-lowering-x2.ll
…
rv64-statepoint-call-lowering.ll
…
rv64-trampoline-cfi.ll
…
rv64-trampoline.ll
…
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
…
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
…
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64p.ll
[LegalizeTypes] Emit FSHL/FSHR from ExpandShiftByConstant when Legal. (#180888)
2026-03-10 15:04:37 -07:00
rv64xandesperf.ll
…
rv64xtheadba.ll
…
rv64xtheadbb.ll
…
rv64xtheadbs.ll
…
rv64zba.ll
…
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
[RISCV] Select (sext_inreg (sra X, C), i8/i16) as slli+srai. (#186956)
2026-03-17 08:01:40 -07:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
…
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
…
rv64zfhmin-half-convert.ll
…
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
rvp-ext-rv32.ll
[RISCV] Select (sext_inreg (sra X, C), i8/i16) as slli+srai. (#186956)
2026-03-17 08:01:40 -07:00
rvp-ext-rv64.ll
[RISCV] Select (sext_inreg (sra X, C), i8/i16) as slli+srai. (#186956)
2026-03-17 08:01:40 -07:00
rvp-narrowing-shift-trunc.ll
[RISCV] Fix crash in combinePExtTruncate for truncate(srl) without MUL/SUB (#186141)
2026-03-13 11:31:04 +08:00
rvp-unaligned-load-store.ll
[RISCV] Partial support for using PPAIRE.B/H to optimize unaligned load sequences. (#183423)
2026-02-25 21:25:23 -08:00
sadd_sat_plus.ll
…
sadd_sat.ll
…
saverestore-scs.ll
…
saverestore.ll
…
scmp.ll
…
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
sdata-sections.ll
…
sdiv-pow2-cmov.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
…
select-cond.ll
…
select-const.ll
…
select-constant-xor.ll
…
select-optimize-multiple.ll
…
select-optimize-multiple.mir
…
select-or.ll
…
select-pseudo-merge-with-stack-adj.ll
…
select-to-and-zext.ll
…
select-zbb.ll
…
select.ll
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
2026-02-20 18:00:07 -08:00
selectcc-to-shiftand.ll
…
selectopt.ll
…
setcc-logic.ll
…
sext-zext-trunc.ll
…
sextw-removal-debug.mir
…
sextw-removal.ll
…
shadowcallstack.ll
…
shift-amount-mod.ll
…
shift-and.ll
…
shift-masked-shamt.ll
…
shifts.ll
…
shl-cttz.ll
…
shl-demanded.ll
…
shlimm-addimm.ll
…
short-forward-branch-load-imm.ll
…
short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
…
short-forward-branch-opt-load.ll
…
short-forward-branch-opt-min-max.ll
…
short-forward-branch-opt-mul.ll
…
short-forward-branch-opt-qcloads.ll
…
short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
short-forward-branch-opt.ll
…
shrinkwrap-jump-table.ll
…
shrinkwrap.ll
…
sifive7-enable-intervals.mir
…
sifive-interrupt-attr-err.ll
…
sifive-interrupt-attr.ll
…
signbit-test.ll
…
signed-truncation-check.ll
…
simplify-condbr.ll
…
sincos-expansion.ll
…
sink-and-fold-crash.mir
…
sink-icmp.ll
…
spacemitx60-sched-copy.mir
…
spill-fill-fold.ll
…
spill-fpr-scalar.ll
…
spir-kernel-cc.ll
…
split-offsets.ll
…
split-sp-adjust.ll
…
split-store.ll
…
split-udiv-by-constant.ll
[LegalizeTypes] Expand UDIV/UREM by constant via chunk summation (#146238)
2026-03-19 17:58:54 +05:30
split-urem-by-constant.ll
[LegalizeTypes] Expand UDIV/UREM by constant via chunk summation (#146238)
2026-03-19 17:58:54 +05:30
sra-xor-sra.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
…
srem-vector-lkk.ll
…
srem.ll
…
srodata.ll
…
ssub_sat_plus.ll
…
ssub_sat.ll
…
stack-clash-prologue-nounwind.ll
…
stack-clash-prologue.ll
…
stack-folding.ll
…
stack-guard-global.ll
…
stack-guard-tls.ll
…
stack-inst-compress.mir
…
stack-offset.ll
…
stack-probing-frame-setup.mir
…
stack-protector-target.ll
…
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-coloring.mir
…
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
…
tagged-globals.ll
…
tail-calls.ll
…
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
tlsdesc-symbol.ll
…
trunc-free.ll
…
trunc-nsw-nuw.ll
…
twoaddr-tied.mir
[TwoAddressInstruction] Iterate through tied regs when analyzing revcopy (#179940)
2026-02-16 11:54:26 +03:00
typepromotion-overflow.ll
…
uadd_sat_plus.ll
…
uadd_sat.ll
…
ucmp.ll
…
udiv-const-optimization.ll
[SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (#181288)
2026-03-06 15:18:34 -08:00
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
…
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
…
urem-lkk.ll
[TargetLowering] Use legally typed shifts to split chunks in expandDIVREMByConstant. (#187567)
2026-03-21 09:31:20 -07:00
urem-seteq-illegal-types.ll
…
urem-vector-lkk.ll
[LegalizeTypes] Expand UDIV/UREM by constant via chunk summation (#146238)
2026-03-19 17:58:54 +05:30
urem.ll
…
usub_sat_plus.ll
…
usub_sat.ll
…
vararg-ilp32e.ll
…
vararg.ll
…
varargs-with-fp-and-second-adj.ll
…
vector-abi.ll
…
vector-tuple-zeroinitializer.ll
…
verify-instr.mir
…
vlenb.ll
…
vmadd-reassociate.ll
…
vscale-demanded-bits.ll
…
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
…
wide-scalar-shift-legalization.ll
…
xaluo.ll
[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)
2026-03-23 16:10:36 +00:00
xandesbfhcvt.ll
…
xandesperf-redundant-copy-elim.ll
…
xcvalu.ll
…
xcvbi.ll
…
xcvbitmanip.ll
…
xcvelw.ll
…
xcvmac.ll
…
xcvmem-heuristic.ll
…
xcvmem.ll
…
xmips-cbop.ll
…
xmips-exectl.ll
…
xqccmp_mvas_mvsa.mir
…
xqccmp-additional-stack.ll
…
xqccmp-callee-saved-gprs.ll
…
xqccmp-cm-popretz.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
xqccmp-cm-push-pop.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
xqccmp-push-pop-popret.ll
…
xqccmp-with-float.ll
…
xqcia.ll
…
xqciac.ll
…
xqcibi-redundant-copy-elim.ll
…
xqcibi.ll
…
xqcibm-cto-clo-brev.ll
…
xqcibm-extract.ll
…
xqcibm-insbi.ll
…
xqcibm-insert.ll
…
xqcibm-regalloc-hints.ll
…
xqcicli.ll
…
xqcicm.ll
…
xqcics.ll
…
xqcilia.ll
…
xqcilo.ll
…
xqcilsm-lwmi-swmi-multiple.mir
…
xqcilsm-lwmi-swmi.mir
…
xqcilsm-memset.ll
…
xqcisls-merge-base-offset-shladd.ll
[RISCV] Fold shladd into Xqcisls scaled load/store in RISCVMergeBaseOffset (#182221)
2026-02-21 15:36:36 +05:30
xqcisls.ll
[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)
2026-03-23 16:10:36 +00:00
xray-attribute-instrumentation.ll
…
xtheadfmemidx.ll
…
xtheadmac.ll
…
xtheadmemidx.ll
[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)
2026-03-23 16:10:36 +00:00
xtheadmempair.ll
…
zalasr-offset-folding.ll
…
zbb-cmp-combine.ll
…
zbb-logic-neg-imm.ll
…
zcb-regalloc-hints.ll
…
zcmp-additional-stack.ll
…
zcmp-cm-popretz.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
zcmp-cm-push-pop.mir
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
2026-02-18 16:42:40 -08:00
zcmp-prolog-epilog-crash.mir
…
zcmp-with-float.ll
…
zdinx-asm-constraint.ll
…
zdinx-boundary-check.ll
…
zdinx-large-spill.mir
…
zdinx-memoperand.ll
…
zdinx-spill.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
zext-with-load-is-free.ll
…
zfh-half-intrinsics-strict.ll
…
zfh-half-intrinsics.ll
…
zfhmin-half-intrinsics-strict.ll
…
zfhmin-half-intrinsics.ll
…
zfhmin-imm.ll
…
zibi.ll
…
zicfilp-indirect-branch.ll
…
zicond-fp-select-zfinx.ll
[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
2026-02-25 14:42:35 -08:00
zicond-opts.ll
…
zilsd-ldst-opt-postra.mir
…
zilsd-ldst-opt-prera.mir
…
zilsd-regalloc-hints.mir
…
zilsd-spill.ll
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
zilsd.ll
…
zmmul.ll
…