shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/RISCV
History
Craig Topper d970e96c53 [RISCV] Add lowering for vp.fptoui and vp.uitofp. 
This is a straightforward extension of D122512 to unsigned integers.
2022-04-01 18:28:46 -07:00
..
AsmParser
[RISCV][NFC] Fix formatting on one line
2022-03-31 13:17:37 +01:00
Disassembler
[Disassember][NFCI] Use strong type for instruction decoder
2022-03-25 18:53:59 -07:00
MCTargetDesc
[RISCV][NFC] Minor formatting fix
2022-03-31 16:15:22 +01:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCV.h
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCV.td
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
RISCVAsmPrinter.cpp
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
2022-03-24 00:48:52 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
RISCVFrameLowering.h
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Use maskedoff to decide mask policy for masked compare and vmsbf/vmsif/vmsof.
2022-03-29 18:05:33 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h
[MachineOutliner] NFC: Hide LRU-related stuff behind helper functions
2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td
[RISCV][NFC] Add immediate tests for the icmp instruction
2022-03-30 02:51:26 +00:00
RISCVInstrInfoA.td
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoF.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoM.td
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
2022-03-31 01:33:17 -07:00
RISCVInstrInfoVPseudos.td
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
2022-03-31 01:33:17 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
2022-04-01 03:09:50 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add VL patterns for vfwmul/vfwadd/vfwsub
2022-03-31 07:08:58 +00:00
RISCVInstrInfoZb.td
[RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)
2022-03-30 16:51:09 +08:00
RISCVInstrInfoZfh.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
RISCVISelDAGToDAG.h
[RISCV] Select unmasked RVV pseudos in a DAG post-process
2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp
[RISCV] Add lowering for vp.fptoui and vp.uitofp.
2022-04-01 18:28:46 -07:00
RISCVISelLowering.h
[RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.
2022-03-28 12:46:36 -07:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
Drop some more global std::maps. NFCI.
2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] add the MC layer support of Zfinx extension
2022-03-02 14:25:19 +08:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSExtWRemoval.cpp
[RISCV] Add more sign-extending ops to MIR sext.w pass.
2022-03-18 18:21:17 +08:00
RISCVSubtarget.cpp
[RISCV] Support 'generic' as a valid CPU name.
2022-03-09 16:43:22 -08:00
RISCVSubtarget.h
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
RISCVTargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 3, fixed assertion crash.
2022-03-23 18:32:17 -07:00
RISCVTargetTransformInfo.h
Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 3, fixed assertion crash.
2022-03-23 18:32:17 -07:00