bbd2ecf9f0
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here https://github.com/riscv/riscv-v-spec/pull/780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
271 lines
9.7 KiB
C++
271 lines
9.7 KiB
C++
//===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISCV specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCVFrameLowering.h"
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#include "RISCVISelLowering.h"
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#include "RISCVInstrInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "RISCVGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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public:
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enum ExtZvl : unsigned {
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NotSet = 0,
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Zvl32b = 32,
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Zvl64b = 64,
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Zvl128b = 128,
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Zvl256b = 256,
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Zvl512b = 512,
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Zvl1024b = 1024,
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Zvl2048b = 2048,
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Zvl4096b = 4096,
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Zvl8192b = 8192,
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Zvl16384b = 16384,
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Zvl32768b = 32768,
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Zvl65536b = 65536
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};
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enum RISCVProcFamilyEnum : uint8_t {
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Others,
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SiFive7,
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};
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private:
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virtual void anchor();
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RISCVProcFamilyEnum RISCVProcFamily = Others;
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bool HasStdExtM = false;
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bool HasStdExtA = false;
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bool HasStdExtF = false;
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bool HasStdExtD = false;
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bool HasStdExtC = false;
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bool HasStdExtZihintpause = false;
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bool HasStdExtZba = false;
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bool HasStdExtZbb = false;
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bool HasStdExtZbc = false;
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bool HasStdExtZbe = false;
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bool HasStdExtZbf = false;
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bool HasStdExtZbm = false;
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bool HasStdExtZbp = false;
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bool HasStdExtZbr = false;
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bool HasStdExtZbs = false;
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bool HasStdExtZbt = false;
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bool HasStdExtV = false;
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bool HasStdExtZve32x = false;
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bool HasStdExtZve32f = false;
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bool HasStdExtZve64x = false;
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bool HasStdExtZve64f = false;
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bool HasStdExtZve64d = false;
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bool HasStdExtZvfh = false;
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bool HasStdExtZfhmin = false;
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bool HasStdExtZfh = false;
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bool HasStdExtZfinx = false;
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bool HasStdExtZdinx = false;
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bool HasStdExtZhinxmin = false;
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bool HasStdExtZhinx = false;
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bool HasStdExtZbkb = false;
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bool HasStdExtZbkc = false;
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bool HasStdExtZbkx = false;
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bool HasStdExtZknd = false;
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bool HasStdExtZkne = false;
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bool HasStdExtZknh = false;
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bool HasStdExtZksed = false;
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bool HasStdExtZksh = false;
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bool HasStdExtZkr = false;
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bool HasStdExtZkn = false;
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bool HasStdExtZks = false;
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bool HasStdExtZkt = false;
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bool HasStdExtZk = false;
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bool HasRV64 = false;
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bool IsRV32E = false;
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bool EnableLinkerRelax = false;
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bool EnableRVCHintInstrs = true;
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bool EnableSaveRestore = false;
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unsigned XLen = 32;
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ExtZvl ZvlLen = ExtZvl::NotSet;
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MVT XLenVT = MVT::i32;
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uint8_t MaxInterleaveFactor = 2;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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BitVector UserReservedRegister;
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RISCVFrameLowering FrameLowering;
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RISCVInstrInfo InstrInfo;
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RISCVRegisterInfo RegInfo;
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RISCVTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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/// Initializes using the passed in CPU and feature strings so that we can
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/// use initializer lists for subtarget initialization.
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RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef CPU,
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StringRef TuneCPU,
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StringRef FS,
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StringRef ABIName);
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public:
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// Initializes the data members to match that of the specified triple.
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
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StringRef FS, StringRef ABIName, const TargetMachine &TM);
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// Parses features string setting specified subtarget options. The
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// definition of this function is auto-generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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const RISCVFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const RISCVRegisterInfo *getRegisterInfo() const override {
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return &RegInfo;
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}
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const RISCVTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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bool enableMachineScheduler() const override { return true; }
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/// Returns RISCV processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
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bool hasStdExtM() const { return HasStdExtM; }
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bool hasStdExtA() const { return HasStdExtA; }
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bool hasStdExtF() const { return HasStdExtF; }
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bool hasStdExtD() const { return HasStdExtD; }
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bool hasStdExtC() const { return HasStdExtC; }
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bool hasStdExtV() const { return HasStdExtV; }
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bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
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bool hasStdExtZba() const { return HasStdExtZba; }
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bool hasStdExtZbb() const { return HasStdExtZbb; }
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bool hasStdExtZbc() const { return HasStdExtZbc; }
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bool hasStdExtZbe() const { return HasStdExtZbe; }
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bool hasStdExtZbf() const { return HasStdExtZbf; }
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bool hasStdExtZbm() const { return HasStdExtZbm; }
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bool hasStdExtZbp() const { return HasStdExtZbp; }
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bool hasStdExtZbr() const { return HasStdExtZbr; }
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bool hasStdExtZbs() const { return HasStdExtZbs; }
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bool hasStdExtZbt() const { return HasStdExtZbt; }
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bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
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bool hasStdExtZvfh() const { return HasStdExtZvfh; }
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bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
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bool hasStdExtZfh() const { return HasStdExtZfh; }
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bool hasStdExtZfinx() const { return HasStdExtZfinx; }
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bool hasStdExtZdinx() const { return HasStdExtZdinx; }
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bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
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bool hasStdExtZhinx() const { return HasStdExtZhinx; }
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bool hasStdExtZbkb() const { return HasStdExtZbkb; }
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bool hasStdExtZbkc() const { return HasStdExtZbkc; }
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bool hasStdExtZbkx() const { return HasStdExtZbkx; }
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bool hasStdExtZknd() const { return HasStdExtZknd; }
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bool hasStdExtZkne() const { return HasStdExtZkne; }
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bool hasStdExtZknh() const { return HasStdExtZknh; }
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bool hasStdExtZksed() const { return HasStdExtZksed; }
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bool hasStdExtZksh() const { return HasStdExtZksh; }
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bool hasStdExtZkr() const { return HasStdExtZkr; }
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bool is64Bit() const { return HasRV64; }
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bool isRV32E() const { return IsRV32E; }
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bool enableLinkerRelax() const { return EnableLinkerRelax; }
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bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
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bool enableSaveRestore() const { return EnableSaveRestore; }
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MVT getXLenVT() const { return XLenVT; }
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unsigned getXLen() const { return XLen; }
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unsigned getFLen() const {
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if (HasStdExtD)
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return 64;
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if (HasStdExtF)
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return 32;
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return 0;
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}
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unsigned getMinVLen() const { return ZvlLen; }
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unsigned getMaxVLen() const { return Zvl65536b; }
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unsigned getRealMinVLen() const {
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unsigned VLen = getMinRVVVectorSizeInBits();
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return VLen == 0 ? getMinVLen() : VLen;
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}
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unsigned getRealMaxVLen() const {
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unsigned VLen = getMaxRVVVectorSizeInBits();
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return VLen == 0 ? getMaxVLen() : VLen;
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}
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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bool isRegisterReservedByUser(Register i) const {
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assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
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return UserReservedRegister[i];
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}
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// Vector codegen related methods.
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bool hasVInstructions() const { return HasStdExtZve32x; }
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bool hasVInstructionsI64() const { return HasStdExtZve64x; }
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bool hasVInstructionsF16() const { return HasStdExtZvfh && HasStdExtZfh; }
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// FIXME: Consider Zfinx in the future
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bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
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// FIXME: Consider Zdinx in the future
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bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
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// F16 and F64 both require F32.
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bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
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unsigned getMaxInterleaveFactor() const {
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return hasVInstructions() ? MaxInterleaveFactor : 1;
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}
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protected:
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// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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public:
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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bool useConstantPoolForLargeInts() const;
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// Maximum cost used for building integers, integers will be put into constant
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// pool if exceeded.
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unsigned getMaxBuildIntsCost() const;
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// Return the known range for the bit length of RVV data registers. A value
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// of 0 means nothing is known about that particular limit beyond what's
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// implied by the architecture.
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unsigned getMaxRVVVectorSizeInBits() const;
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unsigned getMinRVVVectorSizeInBits() const;
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unsigned getMaxLMULForFixedLengthVectors() const;
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unsigned getMaxELENForFixedLengthVectors() const;
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bool useRVVForFixedLengthVectors() const;
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};
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} // End llvm namespace
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#endif
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