a1155ae64d
This patch is a large number of small changes that should hopefully not affect the generated machine code but are still important to get right so that the machine verifier won't complain about them. The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary because without the liveins the used registers are considered undefined by the machine verifier and it will complain about them. Differential Revision: https://reviews.llvm.org/D97172
27 lines
505 B
YAML
27 lines
505 B
YAML
# RUN: llc -O0 %s -o - -march=avr | FileCheck %s
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# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
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--- |
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target triple = "avr--"
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define void @test_lddwrdptrq() {
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entry:
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ret void
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}
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...
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---
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name: test_lddwrdptrq
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $r31r30
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; CHECK-LABEL: test_lddwrdptrq
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; CHECK: ldd r24, Z+10
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; CHECK-NEXT: ldd r25, Z+11
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early-clobber $r25r24 = LDDWRdPtrQ undef $r31r30, 10
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...
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