c1918ad571
This patch expands the support of lowerInterleavedStore to 32x8i stride 4. LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=32) and we plan to include more patterns in the future. To reach our goal of "more patterns". We include two mask creators. The first function creates shuffle's mask equivalent to unpacklo/unpackhi instructions. The other creator creates mask equivalent to a concat of two half vectors(high/low). The patch goal is to optimize the following sequence: At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding each 32 chars: c0, c1, , c31 m0, m1, , m31 y0, y1, , y31 k0, k1, ., k31 And these need to be transposed/interleaved and stored like so: c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 .... Reviewers: dorit Farhana RKSimon guyblank DavidKreitzer Differential Revision: https://reviews.llvm.org/D34601 llvm-svn: 309086
416 lines
16 KiB
C++
416 lines
16 KiB
C++
//===--------- X86InterleavedAccess.cpp ----------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===--------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the X86 implementation of the interleaved accesses
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/// optimization generating X86-specific instructions/intrinsics for
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/// interleaved access groups.
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///
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//===--------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/VectorUtils.h"
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using namespace llvm;
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namespace {
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/// \brief This class holds necessary information to represent an interleaved
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/// access group and supports utilities to lower the group into
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/// X86-specific instructions/intrinsics.
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/// E.g. A group of interleaving access loads (Factor = 2; accessing every
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/// other element)
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/// %wide.vec = load <8 x i32>, <8 x i32>* %ptr
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/// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
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/// %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
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class X86InterleavedAccessGroup {
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/// \brief Reference to the wide-load instruction of an interleaved access
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/// group.
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Instruction *const Inst;
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/// \brief Reference to the shuffle(s), consumer(s) of the (load) 'Inst'.
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ArrayRef<ShuffleVectorInst *> Shuffles;
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/// \brief Reference to the starting index of each user-shuffle.
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ArrayRef<unsigned> Indices;
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/// \brief Reference to the interleaving stride in terms of elements.
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const unsigned Factor;
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/// \brief Reference to the underlying target.
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const X86Subtarget &Subtarget;
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const DataLayout &DL;
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IRBuilder<> &Builder;
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/// \brief Breaks down a vector \p 'Inst' of N elements into \p NumSubVectors
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/// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
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void decompose(Instruction *Inst, unsigned NumSubVectors, VectorType *T,
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SmallVectorImpl<Instruction *> &DecomposedVectors);
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/// \brief Performs matrix transposition on a 4x4 matrix \p InputVectors and
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/// returns the transposed-vectors in \p TransposedVectors.
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/// E.g.
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/// InputVectors:
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/// In-V0 = p1, p2, p3, p4
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/// In-V1 = q1, q2, q3, q4
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/// In-V2 = r1, r2, r3, r4
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/// In-V3 = s1, s2, s3, s4
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/// OutputVectors:
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/// Out-V0 = p1, q1, r1, s1
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/// Out-V1 = p2, q2, r2, s2
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/// Out-V2 = p3, q3, r3, s3
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/// Out-V3 = P4, q4, r4, s4
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void transpose_4x4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix);
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void interleave8bit_32x4(ArrayRef<Instruction *> InputVectors,
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SmallVectorImpl<Value *> &TransposedMatrix);
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public:
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/// In order to form an interleaved access group X86InterleavedAccessGroup
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/// requires a wide-load instruction \p 'I', a group of interleaved-vectors
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/// \p Shuffs, reference to the first indices of each interleaved-vector
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/// \p 'Ind' and the interleaving stride factor \p F. In order to generate
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/// X86-specific instructions/intrinsics it also requires the underlying
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/// target information \p STarget.
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explicit X86InterleavedAccessGroup(Instruction *I,
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ArrayRef<ShuffleVectorInst *> Shuffs,
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ArrayRef<unsigned> Ind, const unsigned F,
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const X86Subtarget &STarget,
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IRBuilder<> &B)
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: Inst(I), Shuffles(Shuffs), Indices(Ind), Factor(F), Subtarget(STarget),
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DL(Inst->getModule()->getDataLayout()), Builder(B) {}
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/// \brief Returns true if this interleaved access group can be lowered into
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/// x86-specific instructions/intrinsics, false otherwise.
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bool isSupported() const;
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/// \brief Lowers this interleaved access group into X86-specific
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/// instructions/intrinsics.
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bool lowerIntoOptimizedSequence();
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};
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} // end anonymous namespace
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bool X86InterleavedAccessGroup::isSupported() const {
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VectorType *ShuffleVecTy = Shuffles[0]->getType();
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Type *ShuffleEltTy = ShuffleVecTy->getVectorElementType();
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unsigned ShuffleElemSize = DL.getTypeSizeInBits(ShuffleEltTy);
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unsigned SupportedNumElem = 4;
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if (ShuffleElemSize == 8)
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SupportedNumElem = 32;
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unsigned WideInstSize;
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// Currently, lowering is supported for the following vectors:
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// 1. 4-element vectors of 64 bits on AVX.
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// 2. 32-element vectors of 8 bits on AVX.
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if (isa<LoadInst>(Inst)) {
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if (DL.getTypeSizeInBits(ShuffleVecTy) !=
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SupportedNumElem * ShuffleElemSize)
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return false;
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WideInstSize = DL.getTypeSizeInBits(Inst->getType());
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} else
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WideInstSize = DL.getTypeSizeInBits(Shuffles[0]->getType());
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if (DL.getTypeSizeInBits(ShuffleEltTy) == 8 && !isa<StoreInst>(Inst))
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return false;
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if (!Subtarget.hasAVX() || Factor != 4 ||
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(ShuffleElemSize != 64 && ShuffleElemSize != 8) ||
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WideInstSize != (Factor * ShuffleElemSize * SupportedNumElem))
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return false;
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return true;
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}
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void X86InterleavedAccessGroup::decompose(
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Instruction *VecInst, unsigned NumSubVectors, VectorType *SubVecTy,
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SmallVectorImpl<Instruction *> &DecomposedVectors) {
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assert((isa<LoadInst>(VecInst) || isa<ShuffleVectorInst>(VecInst)) &&
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"Expected Load or Shuffle");
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Type *VecTy = VecInst->getType();
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(void)VecTy;
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assert(VecTy->isVectorTy() &&
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DL.getTypeSizeInBits(VecTy) >=
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DL.getTypeSizeInBits(SubVecTy) * NumSubVectors &&
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"Invalid Inst-size!!!");
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if (auto *SVI = dyn_cast<ShuffleVectorInst>(VecInst)) {
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Value *Op0 = SVI->getOperand(0);
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Value *Op1 = SVI->getOperand(1);
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// Generate N(= NumSubVectors) shuffles of T(= SubVecTy) type.
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for (unsigned i = 0; i < NumSubVectors; ++i)
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DecomposedVectors.push_back(
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cast<ShuffleVectorInst>(Builder.CreateShuffleVector(
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Op0, Op1,
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createSequentialMask(Builder, Indices[i],
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SubVecTy->getVectorNumElements(), 0))));
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return;
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}
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// Decompose the load instruction.
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LoadInst *LI = cast<LoadInst>(VecInst);
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Type *VecBasePtrTy = SubVecTy->getPointerTo(LI->getPointerAddressSpace());
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Value *VecBasePtr =
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Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
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// Generate N loads of T type.
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for (unsigned i = 0; i < NumSubVectors; i++) {
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// TODO: Support inbounds GEP.
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Value *NewBasePtr = Builder.CreateGEP(VecBasePtr, Builder.getInt32(i));
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Instruction *NewLoad =
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Builder.CreateAlignedLoad(NewBasePtr, LI->getAlignment());
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DecomposedVectors.push_back(NewLoad);
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}
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}
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// Create shuffle mask for concatenation of two half vectors.
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// Low = false: mask generated for the shuffle
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// shuffle(VEC1,VEC2,{NumElement/2, NumElement/2+1, NumElement/2+2...,
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// NumElement-1, NumElement+NumElement/2,
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// NumElement+NumElement/2+1..., 2*NumElement-1})
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// = concat(high_half(VEC1),high_half(VEC2))
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// Low = true: mask generated for the shuffle
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// shuffle(VEC1,VEC2,{0,1,2,...,NumElement/2-1,NumElement,
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// NumElement+1...,NumElement+NumElement/2-1})
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// = concat(low_half(VEC1),low_half(VEC2))
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static void createConcatShuffleMask(int NumElements,
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SmallVectorImpl<uint32_t> &Mask, bool Low) {
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int NumHalfElements = NumElements / 2;
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int Offset = Low ? 0 : NumHalfElements;
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for (int i = 0; i < NumHalfElements; ++i)
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Mask.push_back(i + Offset);
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for (int i = 0; i < NumHalfElements; ++i)
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Mask.push_back(i + Offset + NumElements);
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}
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void X86InterleavedAccessGroup::interleave8bit_32x4(
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ArrayRef<Instruction *> Matrix,
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SmallVectorImpl<Value *> &TransposedMatrix) {
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// Example: Assuming we start from the following vectors:
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// Matrix[0]= c0 c1 c2 c3 c4 ... c31
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// Matrix[1]= m0 m1 m2 m3 m4 ... m31
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// Matrix[2]= y0 y1 y2 y3 y4 ... y31
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// Matrix[3]= k0 k1 k2 k3 k4 ... k31
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TransposedMatrix.resize(4);
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SmallVector<uint32_t, 32> MaskHighTemp;
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SmallVector<uint32_t, 32> MaskLowTemp;
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SmallVector<uint32_t, 32> MaskHighTemp1;
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SmallVector<uint32_t, 32> MaskLowTemp1;
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SmallVector<uint32_t, 32> MaskHighTemp2;
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SmallVector<uint32_t, 32> MaskLowTemp2;
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SmallVector<uint32_t, 32> ConcatLow;
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SmallVector<uint32_t, 32> ConcatHigh;
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// MaskHighTemp and MaskLowTemp built in the vpunpckhbw and vpunpcklbw X86
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// shuffle pattern.
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createUnpackShuffleMask<uint32_t>(MVT::v32i8, MaskHighTemp, false, false);
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createUnpackShuffleMask<uint32_t>(MVT::v32i8, MaskLowTemp, true, false);
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ArrayRef<uint32_t> MaskHigh = makeArrayRef(MaskHighTemp);
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ArrayRef<uint32_t> MaskLow = makeArrayRef(MaskLowTemp);
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// ConcatHigh and ConcatLow built in the vperm2i128 and vinserti128 X86
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// shuffle pattern.
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createConcatShuffleMask(32, ConcatLow, true);
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createConcatShuffleMask(32, ConcatHigh, false);
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ArrayRef<uint32_t> MaskConcatLow = makeArrayRef(ConcatLow);
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ArrayRef<uint32_t> MaskConcatHigh = makeArrayRef(ConcatHigh);
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// MaskHighTemp1 and MaskLowTemp1 built in the vpunpckhdw and vpunpckldw X86
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// shuffle pattern.
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createUnpackShuffleMask<uint32_t>(MVT::v16i16, MaskLowTemp1, true, false);
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createUnpackShuffleMask<uint32_t>(MVT::v16i16, MaskHighTemp1, false, false);
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scaleShuffleMask<uint32_t>(2, makeArrayRef(MaskHighTemp1), MaskHighTemp2);
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scaleShuffleMask<uint32_t>(2, makeArrayRef(MaskLowTemp1), MaskLowTemp2);
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ArrayRef<uint32_t> MaskHighWord = makeArrayRef(MaskHighTemp2);
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ArrayRef<uint32_t> MaskLowWord = makeArrayRef(MaskLowTemp2);
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// IntrVec1Low = c0 m0 c1 m1 ... c7 m7 | c16 m16 c17 m17 ... c23 m23
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// IntrVec1High = c8 m8 c9 m9 ... c15 m15 | c24 m24 c25 m25 ... c31 m31
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// IntrVec2Low = y0 k0 y1 k1 ... y7 k7 | y16 k16 y17 k17 ... y23 k23
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// IntrVec2High = y8 k8 y9 k9 ... y15 k15 | y24 k24 y25 k25 ... y31 k31
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Value *IntrVec1Low =
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Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow);
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Value *IntrVec1High =
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Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh);
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Value *IntrVec2Low =
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Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow);
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Value *IntrVec2High =
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Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh);
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// cmyk4 cmyk5 cmyk6 cmyk7 | cmyk20 cmyk21 cmyk22 cmyk23
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// cmyk12 cmyk13 cmyk14 cmyk15 | cmyk28 cmyk29 cmyk30 cmyk31
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// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk16 cmyk17 cmyk18 cmyk19
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// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk24 cmyk25 cmyk26 cmyk27
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Value *High =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskHighWord);
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Value *High1 =
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Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, MaskHighWord);
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Value *Low =
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Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, MaskLowWord);
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Value *Low1 =
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Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, MaskLowWord);
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// cmyk0 cmyk1 cmyk2 cmyk3 | cmyk4 cmyk5 cmyk6 cmyk7
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// cmyk8 cmyk9 cmyk10 cmyk11 | cmyk12 cmyk13 cmyk14 cmyk15
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// cmyk16 cmyk17 cmyk18 cmyk19 | cmyk20 cmyk21 cmyk22 cmyk23
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// cmyk24 cmyk25 cmyk26 cmyk27 | cmyk28 cmyk29 cmyk30 cmyk31
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TransposedMatrix[0] = Builder.CreateShuffleVector(Low, High, MaskConcatLow);
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TransposedMatrix[1] = Builder.CreateShuffleVector(Low1, High1, MaskConcatLow);
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TransposedMatrix[2] = Builder.CreateShuffleVector(Low, High, MaskConcatHigh);
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TransposedMatrix[3] =
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Builder.CreateShuffleVector(Low1, High1, MaskConcatHigh);
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}
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void X86InterleavedAccessGroup::transpose_4x4(
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ArrayRef<Instruction *> Matrix,
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SmallVectorImpl<Value *> &TransposedMatrix) {
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assert(Matrix.size() == 4 && "Invalid matrix size");
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TransposedMatrix.resize(4);
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// dst = src1[0,1],src2[0,1]
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uint32_t IntMask1[] = {0, 1, 4, 5};
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ArrayRef<uint32_t> Mask = makeArrayRef(IntMask1, 4);
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Value *IntrVec1 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
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Value *IntrVec2 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
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// dst = src1[2,3],src2[2,3]
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uint32_t IntMask2[] = {2, 3, 6, 7};
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Mask = makeArrayRef(IntMask2, 4);
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Value *IntrVec3 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
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Value *IntrVec4 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
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// dst = src1[0],src2[0],src1[2],src2[2]
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uint32_t IntMask3[] = {0, 4, 2, 6};
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Mask = makeArrayRef(IntMask3, 4);
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TransposedMatrix[0] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
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TransposedMatrix[2] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
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// dst = src1[1],src2[1],src1[3],src2[3]
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uint32_t IntMask4[] = {1, 5, 3, 7};
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Mask = makeArrayRef(IntMask4, 4);
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TransposedMatrix[1] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
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TransposedMatrix[3] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
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}
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// Lowers this interleaved access group into X86-specific
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// instructions/intrinsics.
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bool X86InterleavedAccessGroup::lowerIntoOptimizedSequence() {
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SmallVector<Instruction *, 4> DecomposedVectors;
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SmallVector<Value *, 4> TransposedVectors;
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VectorType *ShuffleTy = Shuffles[0]->getType();
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if (isa<LoadInst>(Inst)) {
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// Try to generate target-sized register(/instruction).
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decompose(Inst, Factor, ShuffleTy, DecomposedVectors);
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// Perform matrix-transposition in order to compute interleaved
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// results by generating some sort of (optimized) target-specific
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// instructions.
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transpose_4x4(DecomposedVectors, TransposedVectors);
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// Now replace the unoptimized-interleaved-vectors with the
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// transposed-interleaved vectors.
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for (unsigned i = 0, e = Shuffles.size(); i < e; ++i)
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Shuffles[i]->replaceAllUsesWith(TransposedVectors[Indices[i]]);
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return true;
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}
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Type *ShuffleEltTy = ShuffleTy->getVectorElementType();
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unsigned NumSubVecElems = ShuffleTy->getVectorNumElements() / Factor;
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// Lower the interleaved stores:
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// 1. Decompose the interleaved wide shuffle into individual shuffle
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// vectors.
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decompose(Shuffles[0], Factor, VectorType::get(ShuffleEltTy, NumSubVecElems),
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DecomposedVectors);
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// 2. Transpose the interleaved-vectors into vectors of contiguous
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// elements.
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switch (NumSubVecElems) {
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case 4:
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transpose_4x4(DecomposedVectors, TransposedVectors);
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break;
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case 32:
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interleave8bit_32x4(DecomposedVectors, TransposedVectors);
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break;
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default:
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return false;
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}
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// 3. Concatenate the contiguous-vectors back into a wide vector.
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Value *WideVec = concatenateVectors(Builder, TransposedVectors);
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// 4. Generate a store instruction for wide-vec.
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StoreInst *SI = cast<StoreInst>(Inst);
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Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(),
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SI->getAlignment());
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return true;
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}
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// Lower interleaved load(s) into target specific instructions/
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// intrinsics. Lowering sequence varies depending on the vector-types, factor,
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// number of shuffles and ISA.
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// Currently, lowering is supported for 4x64 bits with Factor = 4 on AVX.
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bool X86TargetLowering::lowerInterleavedLoad(
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LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
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ArrayRef<unsigned> Indices, unsigned Factor) const {
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assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
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"Invalid interleave factor");
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assert(!Shuffles.empty() && "Empty shufflevector input");
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assert(Shuffles.size() == Indices.size() &&
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"Unmatched number of shufflevectors and indices");
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// Create an interleaved access group.
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IRBuilder<> Builder(LI);
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X86InterleavedAccessGroup Grp(LI, Shuffles, Indices, Factor, Subtarget,
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Builder);
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return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
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}
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bool X86TargetLowering::lowerInterleavedStore(StoreInst *SI,
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ShuffleVectorInst *SVI,
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unsigned Factor) const {
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assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
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"Invalid interleave factor");
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assert(SVI->getType()->getVectorNumElements() % Factor == 0 &&
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"Invalid interleaved store");
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// Holds the indices of SVI that correspond to the starting index of each
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// interleaved shuffle.
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SmallVector<unsigned, 4> Indices;
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auto Mask = SVI->getShuffleMask();
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for (unsigned i = 0; i < Factor; i++)
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Indices.push_back(Mask[i]);
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ArrayRef<ShuffleVectorInst *> Shuffles = makeArrayRef(SVI);
|
|
|
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// Create an interleaved access group.
|
|
IRBuilder<> Builder(SI);
|
|
X86InterleavedAccessGroup Grp(SI, Shuffles, Indices, Factor, Subtarget,
|
|
Builder);
|
|
|
|
return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
|
|
}
|