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llvm-project/llvm/test/CodeGen
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Stanislav Mekhanoshin 932f628121 [AMDGPU] new gfx940 fp atomics 
Differential Revision: https://reviews.llvm.org/D121028
2022-03-07 12:32:02 -08:00
..
AArch64
[AArch64] Perform first active true vector combine
2022-03-08 01:10:21 +08:00
AMDGPU
[AMDGPU] new gfx940 fp atomics
2022-03-07 12:32:02 -08:00
ARC
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ARM
[LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.
2022-03-07 11:28:32 -08:00
AVR
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BPF
[BPF] Fix tests that fail if /tmp/t.c exists
2022-02-25 14:55:53 -08:00
CSKY
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Generic
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Hexagon
[Hexagon] Handle v2f16 in build_vector in isel
2022-03-07 11:54:24 -08:00
Inputs
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Lanai
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LoongArch
[LoongArch] Add EncoderMethods for transformed immediate operands
2022-03-07 16:47:26 +08:00
M68k
m68k: Support bit shifts on 64-bit integers
2022-02-12 06:11:49 +08:00
Mips
[Mips] support "sp" named register
2022-03-03 13:53:36 -08:00
MIR
[MIRParser] Diagnose too large align values in MachineMemOperands
2022-02-24 15:32:08 +00:00
MLRegalloc
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MSP430
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NVPTX
[NVPTX] Fix nvvm.match.sync*.i64 intrinsics return type (i64 -> i32)
2022-03-01 12:26:16 +02:00
PowerPC
[PowerPC] Add generic fnmsub intrinsic
2022-03-07 13:00:06 +08:00
RISCV
[RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate.
2022-03-06 19:22:35 -08:00
SPARC
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SystemZ
[SystemZ] [z/OS] Add support for generating huge (1 MiB) stack frames in XPLINK64
2022-02-25 02:37:08 -05:00
Thumb
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
Thumb2
[LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub.
2022-03-07 11:28:32 -08:00
VE
[VE] Split v512.32 load store into interleaved v256.32 ops
2022-03-07 17:38:38 +01:00
WebAssembly
[WebAssembly] Covert llvm/test/MC/WebAssembly/reloc-code.ll to asm. NFC
2022-02-25 07:12:32 -08:00
WinCFGuard
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WinEH
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X86
[x86] add tests for mask+cmp; NFC
2022-03-07 15:14:20 -05:00
XCore
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00