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llvm-project/llvm/test/CodeGen/RISCV
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Zakk Chen 3be907621f [RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate. 
vmsgeu.vi with 0 is always true, but in the masked with mask undisturbed
policy, we still need to keep inactive elelemt which come from maskedoff.

We could return mask directly if it's mask agnostic policy in the future.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121080
2022-03-06 19:22:35 -08:00
..
GlobalISel
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
intrinsics
…
rvv
[RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate.
2022-03-06 19:22:35 -08:00
add-before-shl.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
add-imm.ll
…
addc-adde-sube-subc.ll
…
addcarry.ll
[test][DAGCombine] Add more tests for carry diamond. NFC
2022-01-27 00:25:26 +01:00
addimm-mulimm.ll
[RISCV] Remove tab character from test. Autogenerate CHECK lines. NFC
2022-02-25 11:37:27 -08:00
addrspacecast.ll
…
aext-to-sext.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
align-loops.ll
…
align.ll
…
alloca.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
alu8.ll
[RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization.
2022-01-09 23:37:10 -08:00
alu16.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
alu32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
alu64.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
analyze-branch.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
and.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
atomic-rmw.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
atomic-signext.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
attributes.ll
[RISCV] Recover the implication between Zve* extensions and the V extension.
2022-02-14 15:52:07 +08:00
blockaddress.ll
…
branch-relaxation.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
branch.ll
…
bswap-bitreverse.ll
[RISCV] Custom legalize BITREVERSE with Zbkb.
2022-01-28 23:11:12 -08:00
byval.ll
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
callee-saved-fpr64s.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
callee-saved-gprs.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
calling-conv-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
calling-conv-ilp32.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
calling-conv-lp64.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
…
calls.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
compress-float.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
compress-inline-asm.ll
…
compress.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
copy-frameindex.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
copysign-casts.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
ctlz-cttz-ctpop.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
disable-tail-calls.ll
…
disjoint.ll
…
div-by-constant.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
div-pow2.ll
[RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT
2022-01-11 15:54:35 +08:00
div.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
double-arith-strict.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
double-arith.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
double-bitmanip-dagcombines.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
double-br-fcmp.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
double-calling-conv.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
double-convert-strict.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
double-convert.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
double-fcmp-strict.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
double-fcmp.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
double-frem.ll
[RISCV] Promote f16 frem with Zfh.
2021-11-10 17:35:07 -08:00
double-imm.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
double-intrinsics-strict.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
double-intrinsics.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
double-isnan.ll
…
double-mem.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
double-previous-failure.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
double-round-conv-sat.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
double-round-conv.ll
[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
2022-01-11 09:05:57 -08:00
double-select-fcmp.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
double-stack-spill-restore.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
dwarf-eh.ll
…
elf-preemption.ll
…
exception-pointer-register.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fastcc-float.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
fastcc-int.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
fixups-diff.ll
…
fixups-relax-diff.ll
…
float-arith-strict.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
float-arith.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
float-bit-preserving-dagcombines.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
float-bitmanip-dagcombines.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
float-br-fcmp.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
float-convert-strict.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
float-convert.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
float-fcmp-strict.ll
[RISCV] Add strictfp support for compares.
2022-01-11 20:01:41 -08:00
float-fcmp.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
float-frem.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
float-imm.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
float-intrinsics-strict.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
float-intrinsics.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
float-isnan.ll
…
float-mem.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
float-round-conv-sat.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
float-round-conv.ll
[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
2022-01-11 09:05:57 -08:00
float-select-fcmp.ll
[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
2022-01-10 09:08:29 -08:00
flt-rounds.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
fold-addi-loadstore.ll
[RISCV] Fix a mistake in PostprocessISelDAG
2022-02-25 12:38:31 +00:00
fp16-promote.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
fp128.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
fp-imm.ll
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
fpclamptosat_vec.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
fpclamptosat.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
fpenv.ll
…
frame-info.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
frame.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
frameaddr-returnaddr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
frm-dependency.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
half-arith-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-arith.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
half-bitmanip-dagcombines.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-br-fcmp.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
half-convert-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-convert.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
half-fcmp-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-fcmp.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-frem.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-imm.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-intrinsics.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
half-isnan.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-mem.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-round-conv-sat.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
half-round-conv.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
half-select-fcmp.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
hoist-global-addr-base.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
i32-icmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
iabs.ll
[SelectionDAG][RISCV] Emit a canonical sign bit test from ExpandIntRes_ABS.
2022-03-02 09:47:26 -08:00
imm-cse.ll
…
imm.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
indirectbr.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
2021-12-23 20:32:36 -06:00
inline-asm-S-constraint.ll
…
inline-asm-zfh-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm.ll
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
2022-01-06 08:13:42 -08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
jumptable.ll
[RISCV] Generate 32 bits jumptable entries when code model is small
2022-01-11 18:20:37 +08:00
large-stack.ll
[RISCV] Fix incomplete asm statement parsing
2022-01-19 21:56:21 +00:00
legalize-fneg.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
lit.local.cfg
…
live-sp.mir
[RISCV] Fix invalid kill on callee save
2021-11-02 11:56:54 +00:00
lsr-legaladdimm.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
machine-outliner-patchable.ll
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
2021-12-13 13:24:29 -08:00
machineoutliner-jumptable.mir
…
machineoutliner.mir
…
MachineSink-implicit-x0.mir
Fix minor deficiency in machine-sink.
2021-11-12 08:01:13 +01:00
mattr-invalid-combination.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
mem64.ll
…
mem.ll
…
mir-target-flags.ll
…
module-target-abi2.ll
…
module-target-abi.ll
…
mul.ll
[DAG] try to convert multiply to shift via demanded bits
2022-02-23 12:09:32 -05:00
musttail-call.ll
…
neg-abs.ll
[DAGCombiner] Don't expand (neg (abs x)) if the abs has an additional user.
2022-03-01 07:32:07 -08:00
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
2021-12-23 10:48:28 +05:30
out-of-reach-emergency-slot.mir
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
overflow-intrinsic-optimizations.ll
…
patchable-function-entry.ll
…
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
prefetch.ll
…
readcyclecounter.ll
…
rem.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
remat.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
[NFC][llvm] Inclusive language: reword uses of sanity test and check
2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
rv32zba.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
rv32zbb-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbb-zbp-zbkb.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zbb.ll
[SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
2022-02-20 21:11:23 -08:00
rv32zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbe-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbf-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv32zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbp-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbp-zbkb.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zbp.ll
[SDAG] remove shift that is redundant with part of funnel shift
2022-02-24 11:25:46 -05:00
rv32zbr.ll
…
rv32zbs.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
rv32zbt-intrinsic.ll
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
2022-03-05 21:26:51 -08:00
rv32zbt.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
rv32zknd-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zkne-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zknh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll
[RISCV] Support strict FP conversion operations.
2021-12-23 09:40:58 -06:00
rv64f-float-convert.ll
…
rv64i-complex-float.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
rv64i-demanded-bits.ll
…
rv64i-double-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll
[RISCV] Optimize (sext.w, srli) to sraiw with Zba.
2022-02-28 10:34:35 +08:00
rv64i-single-softfloat.ll
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
rv64zba.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
rv64zbb-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbb-zbp-zbkb.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zbb.ll
[RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X))
2022-03-03 15:42:29 -08:00
rv64zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbe-intrinsic.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zbf-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv64zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbp-intrinsic.ll
[RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.
2022-03-02 09:47:06 -08:00
rv64zbp-zbkb.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zbp.ll
[RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.
2022-03-02 09:47:06 -08:00
rv64zbr.ll
…
rv64zbs.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
rv64zbt-intrinsic.ll
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
2022-03-05 21:26:51 -08:00
rv64zbt.ll
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
rv64zfh-half-convert-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
rv64zfh-half-convert.ll
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
2022-02-24 09:19:01 -08:00
rv64zfh-half-intrinsics-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
rv64zfh-half-intrinsics.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
rv64zknd-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zknd-zkne-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zkne-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zknh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
sadd_sat_plus.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
sadd_sat.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
saverestore.ll
…
scalable-vector-struct.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
[RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)
2022-03-04 22:35:13 -08:00
select-const.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
select-constant-xor.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
select-optimize-multiple.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
select-optimize-multiple.mir
[RISCV] Reorder the vector register allocation order.
2021-10-19 09:30:13 +08:00
select-or.ll
…
selectcc-to-shiftand.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
setcc-logic.ll
…
sext-zext-trunc.ll
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
2022-01-11 02:37:03 +00:00
sextw-removal.ll
[RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval.
2022-02-03 09:40:47 -08:00
shadowcallstack.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
shift-and.ll
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
shifts.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
shlimm-addimm.ll
[RISCV][test] Add tests of (add (shl r, c0), c1)
2021-10-14 14:53:03 +00:00
shrinkwrap.ll
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
sink-icmp.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
spill-fpr-scalar.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
split-offsets.ll
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
split-sp-adjust.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
srem-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
srem-seteq-illegal-types.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
srem-vector-lkk.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
ssub_sat_plus.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
ssub_sat.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
stack-realignment.ll
[RISCV] Reverse the order of loading/storing callee-saved registers.
2021-11-22 23:02:11 +08:00
stack-slot-size.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
stack-store-check.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
subtarget-features-std-ext.ll
…
tail-calls.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
uadd_sat_plus.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
uadd_sat.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
umulo-128-legalisation-lowering.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
unroll-loop-cse.ll
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
2022-02-17 17:27:37 +08:00
urem-lkk.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
urem-seteq-illegal-types.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
urem-vector-lkk.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
usub_sat_plus.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
usub_sat.ll
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
2022-01-12 19:33:44 +00:00
vararg.ll
[RISCV] Use constant pool for large integers
2021-12-31 14:48:48 +08:00
vec3-setcc-crash.ll
[RISCV] Remove experimental prefix from rvv-related extensions.
2022-01-22 20:18:40 -08:00
vector-abi.ll
…
verify-instr.mir
…
wide-mem.ll
…
xaluo.ll
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
zext-with-load-is-free.ll
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
zfh-half-intrinsics-strict.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
zfh-half-intrinsics.ll
[RISCV] update zfh and zfhmin extention to v1.0
2022-01-15 09:21:24 +08:00
zfh-imm.ll
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00