Craig Topper add7b711de

[RISCV] Add RISCVISD opcodes for PSHL/PSRL/PSRA and lower to them. (#184836) ...

We only support splat shift amounts. Previously we checked if the shift
amount was a splat_vector and considered it legal.

I don't think there is a guarantee that the splat_vector will stick
around as a splat_vector. It's safer if we capture the splat and create
a dedicated node with a scalar shift amount.

2026-03-05 12:41:45 -08:00

..

AsmParser

[RISCV] Allow unsigned immediates for pli.h, pli.dh, pli.w (#184554)

2026-03-04 10:07:36 -08:00

Disassembler

[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742)

2026-01-25 00:41:16 +00:00

GISel

[RISCV][GISel] Replace buildInstr with BuildMI (#183714)

2026-03-04 11:21:27 +08:00

MCA

[RISCV] Rename nf->nfields in MC layer. NFC (#179365)

2026-02-02 22:29:24 -08:00

MCTargetDesc

[RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSIGNED->OPERAND_SIMM8 (#184540)

2026-03-03 21:18:12 -08:00

TargetInfo

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CMakeLists.txt

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCV.h

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RISCV.td

[RISCV] Add SpacemiT X100 base scheduling model (#178189)

2026-02-09 11:36:45 +08:00

RISCVAsmPrinter.cpp

[RISCV] Relax codegen predicates for HINT-based instructions (#179872)

2026-03-02 17:24:22 +08:00

RISCVCallingConv.cpp

[RISCV][llvm] Handle calling convention for P extension fixed vectors (#176093)

2026-01-19 12:09:27 +08:00

RISCVCallingConv.h

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RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

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RISCVCombine.td

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RISCVConstantPoolValue.cpp

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RISCVConstantPoolValue.h

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RISCVDeadRegisterDefinitions.cpp

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RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)

2026-03-03 12:38:00 +05:30

RISCVFeatures.td

[RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (#184465)

2026-03-04 08:29:05 -08:00

RISCVFoldMemOffset.cpp

[RISCV] Add Zilsd to RISCVFoldMemOffset (#176544)

2026-01-19 11:19:30 +05:30

RISCVFrameLowering.cpp

[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)

2026-02-18 16:42:40 -08:00

RISCVFrameLowering.h

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RISCVGatherScatterLowering.cpp

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RISCVGISel.td

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RISCVIndirectBranchTracking.cpp

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RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV] Add RISCVII::getTWidenOpNum. NFC (#182335)

2026-02-19 22:11:27 -08:00

RISCVInsertWriteVXRM.cpp

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RISCVInstrFormats.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrFormatsC.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)

2026-01-27 22:55:47 -08:00

RISCVInstrFormatsV.td

[RISCV] Rename RVVConstraint->VS1VS2Constraint. NFC (#182688)

2026-02-23 08:58:14 -08:00

RISCVInstrFormatsXAIF.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571)

2026-01-13 12:54:11 -08:00

RISCVInstrGISel.td

[GISel] Add G_CTLS Opcode and combines, lower to cls(w) (#175069)

2026-01-16 13:22:18 -08:00

RISCVInstrInfo.cpp

[RISCV] Add findCommutedOpIndices support for Zvabd

2026-03-05 11:21:27 +08:00

RISCVInstrInfo.h

[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)

2026-03-04 05:46:26 +00:00

RISCVInstrInfo.td

[RISCV] Use SSLAI for XLen saturating shift left by immediate on RV32. (#184848)

2026-03-05 12:41:19 -08:00

RISCVInstrInfoA.td

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RISCVInstrInfoC.td

[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762)

2026-02-04 13:00:21 -08:00

RISCVInstrInfoD.td

[RISCV] Fix fcanonicalize for Z*inx (#175984)

2026-01-15 23:03:38 -08:00

RISCVInstrInfoF.td

[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)

2026-02-24 10:51:54 -08:00

RISCVInstrInfoM.td

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RISCVInstrInfoP.td

[RISCV] Add RISCVISD opcodes for PSHL/PSRL/PSRA and lower to them. (#184836)

2026-03-05 12:41:45 -08:00

RISCVInstrInfoQ.td

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RISCVInstrInfoSFB.td

[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)

2026-03-03 12:38:00 +05:30

RISCVInstrInfoV.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)

2026-02-24 10:51:54 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Add ComplexPatterns for matching xor/vmnot_vl+vmset_vl. NFC (#182071)

2026-02-19 16:41:48 +00:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add ComplexPatterns for matching xor/vmnot_vl+vmset_vl. NFC (#182071)

2026-02-19 16:41:48 +00:00

RISCVInstrInfoXAIF.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571)

2026-01-13 12:54:11 -08:00

RISCVInstrInfoXAndes.td

[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)

2026-03-03 12:38:00 +05:30

RISCVInstrInfoXCV.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)

2026-01-14 10:22:47 -08:00

RISCVInstrInfoXMips.td

[RISC-V] Reduce code duplication for uimm*_lsb* operands. NFC

2026-01-25 21:45:00 -08:00

RISCVInstrInfoXqccmp.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)

2026-01-27 22:55:47 -08:00

RISCVInstrInfoXqci.td

[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)

2026-03-03 12:38:00 +05:30

RISCVInstrInfoXRivos.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoXSf.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoXSfmm.td

[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)

2026-02-24 10:51:54 -08:00

RISCVInstrInfoXSpacemiT.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)

2026-01-27 22:55:47 -08:00

RISCVInstrInfoZa.td

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RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Treat zext.h as a separate instruction from pack(w) with Zbkb. (#183364)

2026-02-25 20:46:37 -08:00

RISCVInstrInfoZc.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)

2026-01-27 22:55:47 -08:00

RISCVInstrInfoZclsd.td

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RISCVInstrInfoZcmop.td

[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)

2026-02-03 23:39:53 +08:00

RISCVInstrInfoZfa.td

[RISCV] Remove decodeRTZArg. NFC (#177744)

2026-01-24 11:08:57 -08:00

RISCVInstrInfoZfbfmin.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)

2026-01-14 10:22:47 -08:00

RISCVInstrInfoZfh.td

[RISCV] Fix fcanonicalize for Z*inx (#175984)

2026-01-15 23:03:38 -08:00

RISCVInstrInfoZibi.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)

2026-01-14 10:22:47 -08:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)

2026-02-03 23:39:53 +08:00

RISCVInstrInfoZicond.td

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RISCVInstrInfoZilsd.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

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RISCVInstrInfoZvabd.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoZvdot4a8i.td

[RISCV][llvm] Rename zvqdotq to zvdot4a8i (#179393)

2026-02-24 04:44:07 +00:00

RISCVInstrInfoZvfbf.td

[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)

2026-02-26 01:07:25 +08:00

RISCVInstrInfoZvfofp8min.td

[RISCV] Convert some multiclasses in RISCVInstrInfoV.td to classes if they only have one child def. NFC (#181408)

2026-02-13 20:31:49 -08:00

RISCVInstrInfoZvk.td

[RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (#184465)

2026-03-04 08:29:05 -08:00

RISCVInstrPredicates.td

[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well (#172111)

2025-12-16 22:32:20 +00:00

RISCVInterleavedAccess.cpp

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RISCVISelDAGToDAG.cpp

[RISCV] Relax codegen predicates for HINT-based instructions (#179872)

2026-03-02 17:24:22 +08:00

RISCVISelDAGToDAG.h

[RISCV] Add ComplexPatterns for matching xor/vmnot_vl+vmset_vl. NFC (#182071)

2026-02-19 16:41:48 +00:00

RISCVISelLowering.cpp

[RISCV] Add RISCVISD opcodes for PSHL/PSRL/PSRA and lower to them. (#184836)

2026-03-05 12:41:45 -08:00

RISCVISelLowering.h

[LLVM][TTI] Remove the isVScaleKnownToBeAPowerOfTwo hook. (#183292)

2026-02-25 14:09:52 +00:00

RISCVLandingPadSetup.cpp

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RISCVLateBranchOpt.cpp

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RISCVLoadStoreOptimizer.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)

2026-01-23 00:19:03 -08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[RISCV] improve musttail support (#170547)

2026-02-11 17:27:51 +01:00

RISCVMachineScheduler.cpp

[RISCV] Schedule RVV instructions with compatible vtype/vl first

2026-01-12 12:02:39 +08:00

RISCVMachineScheduler.h

[RISCV] Schedule RVV instructions with compatible vtype/vl first

2026-01-12 12:02:39 +08:00

RISCVMacroFusion.td

[RISCV] Add macro fusion support for spacemit-x100 (#178594)

2026-02-04 14:25:52 +08:00

RISCVMakeCompressible.cpp

[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762)

2026-02-04 13:00:21 -08:00

RISCVMergeBaseOffset.cpp

[RISCV] Fold shladd into Xqcisls scaled load/store in RISCVMergeBaseOffset (#182221)

2026-02-21 15:36:36 +05:30

RISCVMoveMerger.cpp

[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)

2026-03-02 20:06:10 -08:00

RISCVOptWInstrs.cpp

[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)

2026-03-03 12:38:00 +05:30

RISCVPassRegistry.def

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RISCVPfmCounters.td

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RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#180677)

2026-02-10 13:39:34 -08:00

RISCVProcessors.td

[RISCV] Add processor definitions for XuanTie C910V2 and C920V2 (#174056)

2026-02-26 14:35:48 +08:00

RISCVProfiles.td

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RISCVPromoteConstant.cpp

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RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)

2026-01-09 14:00:53 +08:00

RISCVRegisterInfo.cpp

[RISCV] Treat zext.h as a separate instruction from pack(w) with Zbkb. (#183364)

2026-02-25 20:46:37 -08:00

RISCVRegisterInfo.h

[RegAlloc] Change the computation of CSRCost (#177226)

2026-02-04 10:08:57 -08:00

RISCVRegisterInfo.td

[RISCV] Add a template function for disassembling LMUL=2/4/8 vector registers. NFC (#177681)

2026-01-23 15:58:55 -08:00

RISCVSchedAndes45.td

[RISCV] Update Andes45 vector reduction scheduling info (#182980)

2026-03-03 08:44:27 +08:00

RISCVSchedGenericOOO.td

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RISCVSchedMIPSP8700.td

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RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[RISCV][NFC] Simplify the vector pipe names in SiFive7 sched model (#181268)

2026-02-13 00:13:53 +00:00

RISCVSchedSiFiveP400.td

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RISCVSchedSiFiveP500.td

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RISCVSchedSiFiveP600.td

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RISCVSchedSiFiveP800.td

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RISCVSchedSpacemitX60.td

[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)

2025-12-18 07:04:42 -08:00

RISCVSchedSpacemitX100.td

[RISCV] Add SpacemiT X100 base scheduling model (#178189)

2026-02-09 11:36:45 +08:00

RISCVSchedSyntacoreSCR1.td

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RISCVSchedSyntacoreSCR7.td

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RISCVSchedSyntacoreSCR345.td

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RISCVSchedTTAscalonX.td

[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X (#178199)

2026-01-27 21:31:51 +00:00

RISCVSchedule.td

[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)

2025-12-18 07:04:42 -08:00

RISCVScheduleV.td

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RISCVScheduleXSf.td

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RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

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RISCVSelectionDAGInfo.cpp

[RISCV][llvm] Rename zvqdotq to zvdot4a8i (#179393)

2026-02-24 04:44:07 +00:00

RISCVSelectionDAGInfo.h

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RISCVSubtarget.cpp

[RISCV] Remove -riscv-enable-p-ext-simd-codegen (#183156)

2026-02-25 08:43:55 -08:00

RISCVSubtarget.h

[RISCV] Support scalar bitreverse using P extension rev instruction. (#183245)

2026-02-25 12:42:59 -08:00

RISCVSystemOperands.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571)

2026-01-13 12:54:11 -08:00

RISCVTargetMachine.cpp

[RISCV] Enable select optimization by default (#178394)

2026-02-10 16:19:01 +08:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[RISCV] Put Large Code Model Constant Pools in .text (#151393)

2026-03-02 13:17:06 -08:00

RISCVTargetObjectFile.h

[RISCV] Put Large Code Model Constant Pools in .text (#151393)

2026-03-02 13:17:06 -08:00

RISCVTargetTransformInfo.cpp

[RISCV] Remove -riscv-enable-p-ext-simd-codegen (#183156)

2026-02-25 08:43:55 -08:00

RISCVTargetTransformInfo.h

[LV] Remove DataAndControlFlowWithoutRuntimeCheck. NFC (#183762)

2026-03-02 21:14:04 +08:00

RISCVVectorMaskDAGMutation.cpp

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RISCVVectorPeephole.cpp

[RISCV] Remove RISCVVectorPeephole::tryToReduceVL (#184297)

2026-03-05 03:58:45 +00:00

RISCVVLOptimizer.cpp

[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)

2026-03-04 05:46:26 +00:00

RISCVVMV0Elimination.cpp

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RISCVVSETVLIInfoAnalysis.cpp

[RISCV] Add RISCVII::getTWidenOpNum. NFC (#182335)

2026-02-19 22:11:27 -08:00

RISCVVSETVLIInfoAnalysis.h

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCVZacasABIFix.cpp

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RISCVZilsdOptimizer.cpp

[llvm][RISCV] Make X0 register pair legal in pre-ra pass (#169164)

2026-01-21 14:13:44 +08:00