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llvm-project/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
Matt Arsenault fdc4274e2f
AMDGPU: Perform libcall recognition to replace fast OpenCL pow (#182135) 
If a float-typed call site is marked with afn, replace the 4
flavors of pow with a faster variant.

This transforms pow, powr, pown, and rootn to __pow_fast,
__powr_fast, __pown_fast, and __rootn_fast if available. Also
attempts to handle all of the same basic folds on the new fast
variants that were already performed with the base forms. This
maintains optimizations with OpenCL when the device libs unsafe
math control library is deleted. This maintains the status quo
of how libcalls work, and only handles 4 new entry points. This
only helps with the elimination of the control library, and not
general libcall emission problems.

This makes no practical difference for HIP, which is the status
quo for libcall optimizations. AMDGPULibCalls recognizes the OpenCL
mangled names. e.g., OpenCL float "pow" is really _Z3powff but the
HIP provided function "powf" is really named _ZL4powfff, and std::pow
with float is _ZL3powff. The pass still runs for HIP, so by accident
if you used the OpenCL mangled function names, this would trigger.

Since the functions cannot yet be relied on from the library,
introduce a temporary module flag check. I'm not planning on emitting
it anywhere and it's a poor substitute for versioning the target.
2026-02-19 11:49:32 +01:00

2222 lines
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s
declare float @_Z4powrff(float, float)
declare <2 x float> @_Z4powrDv2_fS_(<2 x float>, <2 x float>)
declare <3 x float> @_Z4powrDv3_fS_(<3 x float>, <3 x float>)
declare <4 x float> @_Z4powrDv4_fS_(<4 x float>, <4 x float>)
declare <8 x float> @_Z4powrDv8_fS_(<8 x float>, <8 x float>)
declare <16 x float> @_Z4powrDv16_fS_(<16 x float>, <16 x float>)
declare double @_Z4powrdd(double, double)
declare <2 x double> @_Z4powrDv2_dS_(<2 x double>, <2 x double>)
declare <3 x double> @_Z4powrDv3_dS_(<3 x double>, <3 x double>)
declare <4 x double> @_Z4powrDv4_dS_(<4 x double>, <4 x double>)
declare <8 x double> @_Z4powrDv8_dS_(<8 x double>, <8 x double>)
declare <16 x double> @_Z4powrDv16_dS_(<16 x double>, <16 x double>)
declare half @_Z4powrDhDh(half, half)
declare <2 x half> @_Z4powrDv2_DhS_(<2 x half>, <2 x half>)
declare <3 x half> @_Z4powrDv3_DhS_(<3 x half>, <3 x half>)
declare <4 x half> @_Z4powrDv4_DhS_(<4 x half>, <4 x half>)
declare <8 x half> @_Z4powrDv8_DhS_(<8 x half>, <8 x half>)
declare <16 x half> @_Z4powrDv16_DhS_(<16 x half>, <16 x half>)
define float @test_powr_fast_f32(float %x, float %y) {
; CHECK-LABEL: define float @test_powr_fast_f32
; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[Y]], [[__LOG2]]
; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
; CHECK-NEXT: ret float [[__EXP2]]
;
%powr = tail call fast float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_fast_v2f32(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_fast_v2f32
; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[__LOG2:%.*]] = call fast <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast <2 x float> [[Y]], [[__LOG2]]
; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
; CHECK-NEXT: ret <2 x float> [[__EXP2]]
;
%powr = tail call fast <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define float @test_powr_afn_f32(float %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP18]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno float [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0x7FF8000000000000, float [[TMP24]]
; NOPRELINK-NEXT: ret float [[TMP26]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_nnan(float %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_nnan
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan afn float [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select nnan afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn oeq float [[TMP18]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn olt float [[TMP2]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
; NOPRELINK-NEXT: ret float [[TMP24]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32(<2 x float> %x, <2 x float> %y) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32
; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32
; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP11]], <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <2 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[TMP16]], <2 x float> [[TMP9]], <2 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <2 x float> [[TMP18]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <2 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <2 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> [[TMP8]], <2 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP21]], <2 x float> [[TMP23]], <2 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <2 x float> [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP26]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32(<3 x float> %x, <3 x float> %y) {
; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32
; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
; PRELINK-NEXT: ret <3 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <3 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> splat (float 0x7FF0000000000000), <3 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <3 x i1> [[TMP10]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[TMP11]], <3 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <3 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <3 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <3 x i1> [[TMP16]], <3 x float> [[TMP9]], <3 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <3 x float> [[TMP18]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <3 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <3 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <3 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> [[TMP8]], <3 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP21]], <3 x float> [[TMP23]], <3 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <3 x float> [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP26]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> %y)
ret <3 x float> %powr
}
define <4 x float> @test_powr_afn_v4f32(<4 x float> %x, <4 x float> %y) {
; PRELINK-LABEL: define <4 x float> @test_powr_afn_v4f32
; PRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
; PRELINK-NEXT: ret <4 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <4 x float> @test_powr_afn_v4f32
; NOPRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <4 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <4 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <4 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> splat (float 0x7FF0000000000000), <4 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <4 x i1> [[TMP10]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <4 x i1> [[TMP12]], <4 x float> [[TMP11]], <4 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <4 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <4 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <4 x i1> [[TMP16]], <4 x float> [[TMP9]], <4 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <4 x float> [[TMP18]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <4 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <4 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <4 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <4 x i1> [[TMP22]], <4 x float> [[TMP8]], <4 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <4 x i1> [[TMP21]], <4 x float> [[TMP23]], <4 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <4 x float> [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <4 x i1> [[TMP25]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <4 x float> [[TMP26]]
;
%powr = tail call afn <4 x float> @_Z4powrDv4_fS_(<4 x float> %x, <4 x float> %y)
ret <4 x float> %powr
}
define <8 x float> @test_powr_afn_v8f32(<8 x float> %x, <8 x float> %y) {
; PRELINK-LABEL: define <8 x float> @test_powr_afn_v8f32
; PRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
; PRELINK-NEXT: ret <8 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <8 x float> @test_powr_afn_v8f32
; NOPRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <8 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <8 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <8 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> splat (float 0x7FF0000000000000), <8 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <8 x i1> [[TMP10]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <8 x i1> [[TMP12]], <8 x float> [[TMP11]], <8 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <8 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <8 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <8 x i1> [[TMP16]], <8 x float> [[TMP9]], <8 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <8 x float> [[TMP18]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <8 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <8 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <8 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <8 x i1> [[TMP22]], <8 x float> [[TMP8]], <8 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <8 x i1> [[TMP21]], <8 x float> [[TMP23]], <8 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <8 x float> [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <8 x i1> [[TMP25]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <8 x float> [[TMP26]]
;
%powr = tail call afn <8 x float> @_Z4powrDv8_fS_(<8 x float> %x, <8 x float> %y)
ret <8 x float> %powr
}
define <16 x float> @test_powr_afn_v16f32(<16 x float> %x, <16 x float> %y) {
; PRELINK-LABEL: define <16 x float> @test_powr_afn_v16f32
; PRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
; PRELINK-NEXT: ret <16 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <16 x float> @test_powr_afn_v16f32
; NOPRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <16 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <16 x float> [[Y]], [[TMP4]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <16 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> splat (float 0x7FF0000000000000), <16 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <16 x i1> [[TMP10]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <16 x i1> [[TMP12]], <16 x float> [[TMP11]], <16 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <16 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = and <16 x i1> [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <16 x i1> [[TMP16]], <16 x float> [[TMP9]], <16 x float> [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <16 x float> [[TMP18]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <16 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = and <16 x i1> [[TMP19]], [[TMP20]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <16 x float> [[TMP2]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <16 x i1> [[TMP22]], <16 x float> [[TMP8]], <16 x float> [[TMP9]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <16 x i1> [[TMP21]], <16 x float> [[TMP23]], <16 x float> [[TMP17]]
; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <16 x float> [[TMP2]], [[Y]]
; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <16 x i1> [[TMP25]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP24]]
; NOPRELINK-NEXT: ret <16 x float> [[TMP26]]
;
%powr = tail call afn <16 x float> @_Z4powrDv16_fS_(<16 x float> %x, <16 x float> %y)
ret <16 x float> %powr
}
define double @test_powr_afn_f64(double %x, double %y) {
; CHECK-LABEL: define double @test_powr_afn_f64
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn double @_Z4powrdd(double [[X]], double [[Y]])
; CHECK-NEXT: ret double [[POWR]]
;
%powr = tail call afn double @_Z4powrdd(double %x, double %y)
ret double %powr
}
define <2 x double> @test_powr_afn_v2f64(<2 x double> %x, <2 x double> %y) {
; CHECK-LABEL: define <2 x double> @test_powr_afn_v2f64
; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
; CHECK-NEXT: ret <2 x double> [[POWR]]
;
%powr = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %powr
}
define <3 x double> @test_powr_afn_v3f64(<3 x double> %x, <3 x double> %y) {
; CHECK-LABEL: define <3 x double> @test_powr_afn_v3f64
; CHECK-SAME: (<3 x double> [[X:%.*]], <3 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <3 x double> @_Z4powrDv3_dS_(<3 x double> [[X]], <3 x double> [[Y]])
; CHECK-NEXT: ret <3 x double> [[POWR]]
;
%powr = tail call afn <3 x double> @_Z4powrDv3_dS_(<3 x double> %x, <3 x double> %y)
ret <3 x double> %powr
}
define <4 x double> @test_powr_afn_v4f64(<4 x double> %x, <4 x double> %y) {
; CHECK-LABEL: define <4 x double> @test_powr_afn_v4f64
; CHECK-SAME: (<4 x double> [[X:%.*]], <4 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <4 x double> @_Z4powrDv4_dS_(<4 x double> [[X]], <4 x double> [[Y]])
; CHECK-NEXT: ret <4 x double> [[POWR]]
;
%powr = tail call afn <4 x double> @_Z4powrDv4_dS_(<4 x double> %x, <4 x double> %y)
ret <4 x double> %powr
}
define <8 x double> @test_powr_afn_v8f64(<8 x double> %x, <8 x double> %y) {
; CHECK-LABEL: define <8 x double> @test_powr_afn_v8f64
; CHECK-SAME: (<8 x double> [[X:%.*]], <8 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <8 x double> @_Z4powrDv8_dS_(<8 x double> [[X]], <8 x double> [[Y]])
; CHECK-NEXT: ret <8 x double> [[POWR]]
;
%powr = tail call afn <8 x double> @_Z4powrDv8_dS_(<8 x double> %x, <8 x double> %y)
ret <8 x double> %powr
}
define <16 x double> @test_powr_afn_v16f64(<16 x double> %x, <16 x double> %y) {
; CHECK-LABEL: define <16 x double> @test_powr_afn_v16f64
; CHECK-SAME: (<16 x double> [[X:%.*]], <16 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <16 x double> @_Z4powrDv16_dS_(<16 x double> [[X]], <16 x double> [[Y]])
; CHECK-NEXT: ret <16 x double> [[POWR]]
;
%powr = tail call afn <16 x double> @_Z4powrDv16_dS_(<16 x double> %x, <16 x double> %y)
ret <16 x double> %powr
}
define half @test_powr_afn_f16(half %x, half %y) {
; CHECK-LABEL: define half @test_powr_afn_f16
; CHECK-SAME: (half [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn half @_Z4powrDhDh(half [[X]], half [[Y]])
; CHECK-NEXT: ret half [[POWR]]
;
%powr = tail call afn half @_Z4powrDhDh(half %x, half %y)
ret half %powr
}
define <2 x half> @test_powr_afn_v2f16(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: define <2 x half> @test_powr_afn_v2f16
; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
; CHECK-NEXT: ret <2 x half> [[POWR]]
;
%powr = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %powr
}
define <3 x half> @test_powr_afn_v3f16(<3 x half> %x, <3 x half> %y) {
; CHECK-LABEL: define <3 x half> @test_powr_afn_v3f16
; CHECK-SAME: (<3 x half> [[X:%.*]], <3 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <3 x half> @_Z4powrDv3_DhS_(<3 x half> [[X]], <3 x half> [[Y]])
; CHECK-NEXT: ret <3 x half> [[POWR]]
;
%powr = tail call afn <3 x half> @_Z4powrDv3_DhS_(<3 x half> %x, <3 x half> %y)
ret <3 x half> %powr
}
define <4 x half> @test_powr_afn_v4f16(<4 x half> %x, <4 x half> %y) {
; CHECK-LABEL: define <4 x half> @test_powr_afn_v4f16
; CHECK-SAME: (<4 x half> [[X:%.*]], <4 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <4 x half> @_Z4powrDv4_DhS_(<4 x half> [[X]], <4 x half> [[Y]])
; CHECK-NEXT: ret <4 x half> [[POWR]]
;
%powr = tail call afn <4 x half> @_Z4powrDv4_DhS_(<4 x half> %x, <4 x half> %y)
ret <4 x half> %powr
}
define <8 x half> @test_powr_afn_v8f16(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: define <8 x half> @test_powr_afn_v8f16
; CHECK-SAME: (<8 x half> [[X:%.*]], <8 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <8 x half> @_Z4powrDv8_DhS_(<8 x half> [[X]], <8 x half> [[Y]])
; CHECK-NEXT: ret <8 x half> [[POWR]]
;
%powr = tail call afn <8 x half> @_Z4powrDv8_DhS_(<8 x half> %x, <8 x half> %y)
ret <8 x half> %powr
}
define <16 x half> @test_powr_afn_v16f16(<16 x half> %x, <16 x half> %y) {
; CHECK-LABEL: define <16 x half> @test_powr_afn_v16f16
; CHECK-SAME: (<16 x half> [[X:%.*]], <16 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call afn <16 x half> @_Z4powrDv16_DhS_(<16 x half> [[X]], <16 x half> [[Y]])
; CHECK-NEXT: ret <16 x half> [[POWR]]
;
%powr = tail call afn <16 x half> @_Z4powrDv16_DhS_(<16 x half> %x, <16 x half> %y)
ret <16 x half> %powr
}
define float @test_powr_f32(float %x, float %y) {
; CHECK-LABEL: define float @test_powr_f32
; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
; CHECK-NEXT: ret float [[POWR]]
;
%powr = tail call float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_f32_nnan(float %x, float %y) {
; CHECK-LABEL: define float @test_powr_f32_nnan
; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call nnan float @_Z4powrff(float [[X]], float [[Y]])
; CHECK-NEXT: ret float [[POWR]]
;
%powr = tail call nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_v2f32(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_v2f32
; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
; CHECK-NEXT: ret <2 x float> [[POWR]]
;
%powr = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define <3 x float> @test_powr_v3f32(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: define <3 x float> @test_powr_v3f32
; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <3 x float> @_Z4powrDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
; CHECK-NEXT: ret <3 x float> [[POWR]]
;
%powr = tail call <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> %y)
ret <3 x float> %powr
}
define <4 x float> @test_powr_v4f32(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: define <4 x float> @test_powr_v4f32
; CHECK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <4 x float> @_Z4powrDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
; CHECK-NEXT: ret <4 x float> [[POWR]]
;
%powr = tail call <4 x float> @_Z4powrDv4_fS_(<4 x float> %x, <4 x float> %y)
ret <4 x float> %powr
}
define <8 x float> @test_powr_v8f32(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: define <8 x float> @test_powr_v8f32
; CHECK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <8 x float> @_Z4powrDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
; CHECK-NEXT: ret <8 x float> [[POWR]]
;
%powr = tail call <8 x float> @_Z4powrDv8_fS_(<8 x float> %x, <8 x float> %y)
ret <8 x float> %powr
}
define <16 x float> @test_powr_v16f32(<16 x float> %x, <16 x float> %y) {
; CHECK-LABEL: define <16 x float> @test_powr_v16f32
; CHECK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <16 x float> @_Z4powrDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
; CHECK-NEXT: ret <16 x float> [[POWR]]
;
%powr = tail call <16 x float> @_Z4powrDv16_fS_(<16 x float> %x, <16 x float> %y)
ret <16 x float> %powr
}
define double @test_powr_f64(double %x, double %y) {
; CHECK-LABEL: define double @test_powr_f64
; CHECK-SAME: (double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call double @_Z4powrdd(double [[X]], double [[Y]])
; CHECK-NEXT: ret double [[POWR]]
;
%powr = tail call double @_Z4powrdd(double %x, double %y)
ret double %powr
}
define <2 x double> @test_powr_v2f64(<2 x double> %x, <2 x double> %y) {
; CHECK-LABEL: define <2 x double> @test_powr_v2f64
; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
; CHECK-NEXT: ret <2 x double> [[POWR]]
;
%powr = tail call <2 x double> @_Z4powrDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %powr
}
define <3 x double> @test_powr_v3f64(<3 x double> %x, <3 x double> %y) {
; CHECK-LABEL: define <3 x double> @test_powr_v3f64
; CHECK-SAME: (<3 x double> [[X:%.*]], <3 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <3 x double> @_Z4powrDv3_dS_(<3 x double> [[X]], <3 x double> [[Y]])
; CHECK-NEXT: ret <3 x double> [[POWR]]
;
%powr = tail call <3 x double> @_Z4powrDv3_dS_(<3 x double> %x, <3 x double> %y)
ret <3 x double> %powr
}
define <4 x double> @test_powr_v4f64(<4 x double> %x, <4 x double> %y) {
; CHECK-LABEL: define <4 x double> @test_powr_v4f64
; CHECK-SAME: (<4 x double> [[X:%.*]], <4 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <4 x double> @_Z4powrDv4_dS_(<4 x double> [[X]], <4 x double> [[Y]])
; CHECK-NEXT: ret <4 x double> [[POWR]]
;
%powr = tail call <4 x double> @_Z4powrDv4_dS_(<4 x double> %x, <4 x double> %y)
ret <4 x double> %powr
}
define <8 x double> @test_powr_v8f64(<8 x double> %x, <8 x double> %y) {
; CHECK-LABEL: define <8 x double> @test_powr_v8f64
; CHECK-SAME: (<8 x double> [[X:%.*]], <8 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <8 x double> @_Z4powrDv8_dS_(<8 x double> [[X]], <8 x double> [[Y]])
; CHECK-NEXT: ret <8 x double> [[POWR]]
;
%powr = tail call <8 x double> @_Z4powrDv8_dS_(<8 x double> %x, <8 x double> %y)
ret <8 x double> %powr
}
define <16 x double> @test_powr_v16f64(<16 x double> %x, <16 x double> %y) {
; CHECK-LABEL: define <16 x double> @test_powr_v16f64
; CHECK-SAME: (<16 x double> [[X:%.*]], <16 x double> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <16 x double> @_Z4powrDv16_dS_(<16 x double> [[X]], <16 x double> [[Y]])
; CHECK-NEXT: ret <16 x double> [[POWR]]
;
%powr = tail call <16 x double> @_Z4powrDv16_dS_(<16 x double> %x, <16 x double> %y)
ret <16 x double> %powr
}
define half @test_powr_f16(half %x, half %y) {
; CHECK-LABEL: define half @test_powr_f16
; CHECK-SAME: (half [[X:%.*]], half [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call half @_Z4powrDhDh(half [[X]], half [[Y]])
; CHECK-NEXT: ret half [[POWR]]
;
%powr = tail call half @_Z4powrDhDh(half %x, half %y)
ret half %powr
}
define <2 x half> @test_powr_v2f16(<2 x half> %x, <2 x half> %y) {
; CHECK-LABEL: define <2 x half> @test_powr_v2f16
; CHECK-SAME: (<2 x half> [[X:%.*]], <2 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
; CHECK-NEXT: ret <2 x half> [[POWR]]
;
%powr = tail call <2 x half> @_Z4powrDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %powr
}
define <3 x half> @test_powr_v3f16(<3 x half> %x, <3 x half> %y) {
; CHECK-LABEL: define <3 x half> @test_powr_v3f16
; CHECK-SAME: (<3 x half> [[X:%.*]], <3 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <3 x half> @_Z4powrDv3_DhS_(<3 x half> [[X]], <3 x half> [[Y]])
; CHECK-NEXT: ret <3 x half> [[POWR]]
;
%powr = tail call <3 x half> @_Z4powrDv3_DhS_(<3 x half> %x, <3 x half> %y)
ret <3 x half> %powr
}
define <4 x half> @test_powr_v4f16(<4 x half> %x, <4 x half> %y) {
; CHECK-LABEL: define <4 x half> @test_powr_v4f16
; CHECK-SAME: (<4 x half> [[X:%.*]], <4 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <4 x half> @_Z4powrDv4_DhS_(<4 x half> [[X]], <4 x half> [[Y]])
; CHECK-NEXT: ret <4 x half> [[POWR]]
;
%powr = tail call <4 x half> @_Z4powrDv4_DhS_(<4 x half> %x, <4 x half> %y)
ret <4 x half> %powr
}
define <8 x half> @test_powr_v8f16(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: define <8 x half> @test_powr_v8f16
; CHECK-SAME: (<8 x half> [[X:%.*]], <8 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <8 x half> @_Z4powrDv8_DhS_(<8 x half> [[X]], <8 x half> [[Y]])
; CHECK-NEXT: ret <8 x half> [[POWR]]
;
%powr = tail call <8 x half> @_Z4powrDv8_DhS_(<8 x half> %x, <8 x half> %y)
ret <8 x half> %powr
}
define <16 x half> @test_powr_v16f16(<16 x half> %x, <16 x half> %y) {
; CHECK-LABEL: define <16 x half> @test_powr_v16f16
; CHECK-SAME: (<16 x half> [[X:%.*]], <16 x half> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <16 x half> @_Z4powrDv16_DhS_(<16 x half> [[X]], <16 x half> [[Y]])
; CHECK-NEXT: ret <16 x half> [[POWR]]
;
%powr = tail call <16 x half> @_Z4powrDv16_DhS_(<16 x half> %x, <16 x half> %y)
ret <16 x half> %powr
}
define float @test_powr_afn_f32_minsize(float %x, float %y) #0 {
; PRELINK-LABEL: define float @test_powr_afn_f32_minsize
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_minsize
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]])
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_nnan_minsize(float %x, float %y) #0 {
; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_minsize
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_minsize
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]])
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_noinline(float %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_noinline
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR4:[0-9]+]]
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_noinline
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR3:[0-9]+]]
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y) #1
ret float %powr
}
define float @test_powr_afn_f32_nnan_noinline(float %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_noinline
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR4]]
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_noinline
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR3]]
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y) #1
ret float %powr
}
define float @test_powr_afn_f32_strictfp(float %x, float %y) #2 {
; PRELINK-LABEL: define float @test_powr_afn_f32_strictfp
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan nsz afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR1]]
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_strictfp
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan nsz afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR1]]
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nsz nnan float @_Z4powrff(float %x, float %y) #2
ret float %powr
}
define float @test_powr_fast_f32_nobuiltin(float %x, float %y) {
; PRELINK-LABEL: define float @test_powr_fast_f32_nobuiltin
; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call fast float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_fast_f32_nobuiltin
; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[POWR:%.*]] = tail call fast float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR4:[0-9]+]]
; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call fast float @_Z4powrff(float %x, float %y) #3
ret float %powr
}
define float @test_powr_afn_f32_poison(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_poison
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float poison)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_poison
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: ret float poison
;
%powr = tail call afn float @_Z4powrff(float %x, float poison)
ret float %powr
}
define float @test_powr_afn_f32_0.0(float %x) {
; CHECK-LABEL: define float @test_powr_afn_f32_0.0
; CHECK-SAME: (float [[X:%.*]]) {
; CHECK-NEXT: ret float 1.000000e+00
;
%powr = tail call afn float @_Z4powrff(float %x, float 0.0)
ret float %powr
}
define float @test_powr_afn_f32_neg0.0(float %x) {
; CHECK-LABEL: define float @test_powr_afn_f32_neg0.0
; CHECK-SAME: (float [[X:%.*]]) {
; CHECK-NEXT: ret float 1.000000e+00
;
%powr = tail call afn float @_Z4powrff(float %x, float -0.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_0.0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.0
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float 0.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg0.0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.0
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -0.0, float -0.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0.000000e+00, float -0.000000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0.000000e+00, float -0.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn ueq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float -0.0>)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_0.0_splat_undef(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.0_splat_undef
; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; CHECK-NEXT: ret <3 x float> splat (float 1.000000e+00)
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float 0.0, float poison, float 0.0>)
ret <3 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_neg0.0_splat_undef(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.0_splat_undef
; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; CHECK-NEXT: ret <3 x float> splat (float 1.000000e+00)
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float -0.0, float poison, float -0.0>)
ret <3 x float> %powr
}
define float @test_powr_afn_f32_0.5(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_0.5
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
; PRELINK-NEXT: ret float [[__POW2SQRT]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_0.5
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 5.000000e-01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0.5)
ret float %powr
}
define float @test_powr_afn_f32_neg0.5(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg0.5
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
; PRELINK-NEXT: ret float [[__POW2RSQRT]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg0.5
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -5.000000e-01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -0.5)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_0.5(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
; PRELINK-NEXT: ret <2 x float> [[__POW2SQRT]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 5.000000e-01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg0.5(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
; PRELINK-NEXT: ret <2 x float> [[__POW2RSQRT]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -5.000000e-01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 5.000000e-01, float -5.000000e-01>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 5.000000e-01, float -5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float -0.5>)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <3 x float> @_Z4sqrtDv3_f(<3 x float> [[X]])
; PRELINK-NEXT: ret <3 x float> [[__POW2SQRT]]
;
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float 5.000000e-01, float poison, float 5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
ret <3 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <3 x float> @_Z5rsqrtDv3_f(<3 x float> [[X]])
; PRELINK-NEXT: ret <3 x float> [[__POW2RSQRT]]
;
; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float -5.000000e-01, float poison, float -5.000000e-01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float -0.5, float poison, float -0.5>)
ret <3 x float> %powr
}
define float @test_powr_afn_f32_1.0(float %x) {
; CHECK-LABEL: define float @test_powr_afn_f32_1.0
; CHECK-SAME: (float [[X:%.*]]) {
; CHECK-NEXT: ret float [[X]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 1.0)
ret float %powr
}
define float @test_powr_afn_f32_neg1.0(float %x) {
; CHECK-LABEL: define float @test_powr_afn_f32_neg1.0
; CHECK-SAME: (float [[X:%.*]]) {
; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
; CHECK-NEXT: ret float [[__POWRECIP]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -1.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_1.0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_1.0
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
; CHECK-NEXT: ret <2 x float> [[X]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float 1.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg1.0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg1.0
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT: ret <2 x float> [[__POWRECIP]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -1.0, float -1.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.000000e+00, float -1.000000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.000000e+00, float -1.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float -1.0>)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_1.0_splat_undef(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_1.0_splat_undef
; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; CHECK-NEXT: ret <3 x float> [[X]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float 1.0, float poison, float 1.0>)
ret <3 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_neg1.0_splat_undef(<3 x float> %x, <3 x float> %y) {
; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg1.0_splat_undef
; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn <3 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT: ret <3 x float> [[__POWRECIP]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float -1.0, float poison, float -1.0>)
ret <3 x float> %powr
}
define float @test_powr_afn_f32_2.0(float %x) {
; CHECK-LABEL: define float @test_powr_afn_f32_2.0
; CHECK-SAME: (float [[X:%.*]]) {
; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
; CHECK-NEXT: ret float [[__POW2]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 2.0)
ret float %powr
}
define float @test_powr_afn_f32_neg2.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg2.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -2.000000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg2.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -2.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -2.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_2.0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_2.0
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
; CHECK-NEXT: [[__POW2:%.*]] = fmul afn <2 x float> [[X]], [[X]]
; CHECK-NEXT: ret <2 x float> [[__POW2]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float 2.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg2.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -2.000000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -2.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 2.000000e+00, float -2.000000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 2.000000e+00, float -2.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float -2.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_3.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_3.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 3.000000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 3.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 3.0)
ret float %powr
}
define float @test_powr_afn_f32_neg3.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg3.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -3.000000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -3.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -3.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_3.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.000000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 3.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg3.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -3.000000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -3.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -3.0, float -3.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 3.000000e+00, float -3.000000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 3.000000e+00, float -3.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float -3.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_3.99(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_3.99
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0x400FEB8520000000)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0x400FEB8520000000
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0x400FEB8520000000)
ret float %powr
}
define float @test_powr_afn_f32_neg3.99(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0xC00FEB8520000000)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0xC00FEB8520000000
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0xC00FEB8520000000)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0x400FEB8520000000))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0x400FEB8520000000)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0x400FEB8520000000>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0xC00FEB8520000000))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0xC00FEB8520000000)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0xC00FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0x400FEB8520000000, float 0xC00FEB8520000000>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_8.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_8.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 8.000000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_8.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 8.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 8.0)
ret float %powr
}
define float @test_powr_afn_f32_neg8.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg8.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -8.000000e+00)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg8.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -8.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -8.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_8.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 8.000000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 8.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float 8.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg8.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -8.000000e+00))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -8.000000e+00)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -8.0, float -8.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 8.000000e+00, float -8.000000e+00>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 8.000000e+00, float -8.000000e+00>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float -8.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_12.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_12.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 1.200000e+01)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_12.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.200000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 12.0)
ret float %powr
}
define float @test_powr_afn_f32_neg12.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg12.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -1.200000e+01)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg12.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.200000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -12.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_12.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 1.200000e+01))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.200000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float 12.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg12.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -1.200000e+01))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.200000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -12.0, float -12.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.200000e+01, float -1.200000e+01>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.200000e+01, float -1.200000e+01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float -12.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_13.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_13.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 1.300000e+01)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_13.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.300000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 13.0)
ret float %powr
}
define float @test_powr_afn_f32_neg13.0(float %x) {
; PRELINK-LABEL: define float @test_powr_afn_f32_neg13.0
; PRELINK-SAME: (float [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -1.300000e+01)
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg13.0
; NOPRELINK-SAME: (float [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.300000e+01
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -13.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_13.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 1.300000e+01))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.300000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 13.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg13.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -1.300000e+01))
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.300000e+01)
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -13.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.300000e+01, float -1.300000e+01>)
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.300000e+01, float -1.300000e+01>
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float -13.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_x_known_positive
; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_x_known_positive
; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn float [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[X]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq float [[TMP16]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
; NOPRELINK-NEXT: ret float [[TMP22]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
; CHECK-LABEL: define float @test_powr_afn_f32_nnan_ninf_x_known_positive
; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
; CHECK-NEXT: ret float [[__EXP2]]
;
%powr = tail call afn nnan ninf float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive
; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive
; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn <2 x float> [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP22]]
;
%powr = tail call afn nnan <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_nnan_ninf_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_ninf_x_known_positive
; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[Y]], [[__LOG2]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
; CHECK-NEXT: ret <2 x float> [[__EXP2]]
;
%powr = tail call afn nnan ninf <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define float @test_powr_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
; CHECK-LABEL: define float @test_powr_f32_x_known_positive
; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
; CHECK-NEXT: ret float [[POWR]]
;
%powr = tail call float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_x_known_positive
; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_x_known_positive
; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn float [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[X]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq float [[TMP16]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt float [[X]], 1.000000e+00
; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno float [[X]], [[Y]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP23]], float 0x7FF8000000000000, float [[TMP22]]
; NOPRELINK-NEXT: ret float [[TMP24]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_v2f32_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_v2f32_x_known_positive
; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; CHECK-NEXT: [[POWR:%.*]] = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
; CHECK-NEXT: ret <2 x float> [[POWR]]
;
%powr = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_x_known_positive
; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_x_known_positive
; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn <2 x float> [[Y]], [[TMP2]]
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt <2 x float> [[X]], splat (float 1.000000e+00)
; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno <2 x float> [[X]], [[Y]]
; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP22]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define float @test_powr_f32_known_integral_sitofp(float %x, i32 %y) {
; CHECK-LABEL: define float @test_powr_f32_known_integral_sitofp
; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
; CHECK-NEXT: [[POWR:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y_CAST]])
; CHECK-NEXT: ret float [[POWR]]
;
%y.cast = sitofp i32 %y to float
%powr = tail call float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define float @test_powr_afn_f32_known_integral_sitofp(float %x, i32 %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp
; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp
; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP17]]
; NOPRELINK-NEXT: ret float [[TMP19]]
;
%y.cast = sitofp i32 %y to float
%powr = tail call afn float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define float @test_powr_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y) {
; CHECK-LABEL: define float @test_powr_afn_nnan_ninf_f32_known_integral_sitofp
; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
; CHECK-NEXT: ret float [[__EXP2]]
;
%y.cast = sitofp i32 %y to float
%powr = tail call afn nnan ninf float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define float @test_powr_f32_known_integral_uitofp(float %x, i32 %y) {
; CHECK-LABEL: define float @test_powr_f32_known_integral_uitofp
; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
; CHECK-NEXT: [[POWR:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y_CAST]])
; CHECK-NEXT: ret float [[POWR]]
;
%y.cast = uitofp i32 %y to float
%powr = tail call float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define float @test_powr_afn_f32_known_integral_uitofp(float %x, i32 %y) {
; PRELINK-LABEL: define float @test_powr_afn_f32_known_integral_uitofp
; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
; PRELINK-NEXT: ret float [[POWR]]
;
; NOPRELINK-LABEL: define float @test_powr_afn_f32_known_integral_uitofp
; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF8000000000000, float 0.000000e+00
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float [[TMP8]], float [[TMP6]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[Y]], 0
; NOPRELINK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn i1 [[TMP13]], float 0x7FF0000000000000, float [[TMP10]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
; NOPRELINK-NEXT: ret float [[TMP16]]
;
%y.cast = uitofp i32 %y to float
%powr = tail call afn float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define float @test_powr_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y) {
; CHECK-LABEL: define float @test_powr_afn_nnan_ninf_f32_known_integral_uitofp
; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
; CHECK-NEXT: ret float [[__EXP2]]
;
%y.cast = uitofp i32 %y to float
%powr = tail call afn nnan ninf float @_Z4powrff(float %x, float %y.cast)
ret float %powr
}
define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x float> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_sitofp
; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
; CHECK-NEXT: ret <2 x float> [[__EXP2]]
;
%y.cast = sitofp <2 x i32> %y to <2 x float>
%powr = tail call afn nnan ninf <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
ret <2 x float> %powr
}
define <2 x float> @test_powr_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_v2f32_known_integral_uitofp
; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
; CHECK-NEXT: [[POWR:%.*]] = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y_CAST]])
; CHECK-NEXT: ret <2 x float> [[POWR]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%powr = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp
; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y_CAST]])
; PRELINK-NEXT: ret <2 x float> [[POWR]]
;
; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp
; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[Y_CAST]]
; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> zeroinitializer
; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> [[TMP8]], <2 x float> [[TMP6]]
; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT: [[TMP13:%.*]] = and <2 x i1> [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP10]]
; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: ret <2 x float> [[TMP16]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_uitofp
; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]]
; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
; CHECK-NEXT: ret <2 x float> [[__EXP2]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%powr = tail call afn nnan ninf <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
ret <2 x float> %powr
}
attributes #0 = { minsize }
attributes #1 = { noinline }
attributes #2 = { strictfp }
attributes #3 = { nobuiltin }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
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