21c1ba16ed
Artificial registers were added in
eb0c510ecde667cd911682cc1e855f73f341d134
as a means of giving super-registers heavier weights than that
of their subregisters, even when they only contain a single
physical subregister.
Artifical registers thus do exist in code and participate in
register unit weight calculations, but are not supposed to be
available for register allocation.
This patch completes the support for artificial registers to:
- Ignore artificial registers when joining register unit uber
sets. Artificial registers may be members of classes that
together include registers and their sub-registers, making it
impossible to compute normalised weights for uber sets they
belong to.
We have a use case downstream relying on this being supported,
which allows to avoid introducing a large number of additional
register classes.
- Not generate purely artificial register class intersections.
It is critical not to have such classes, as the common LLVM
codegen infrastructure will try to use them to constrain
classes of virtual registers instead of producing COPYs
whenever both the source and target register classes contain
the same artificial registers.
- Not generate sub-classes where classes with the same
non-artificial members already exist. This is mostly for
convenience. For example, the HI16-capable subset of AMDGPU's
AV_32 is VGPR_32, except VGPR_32 also contains the artificial
staging registers. If the staging registers are not ignored,
we'll end up having an additional generated register class,
AV_32_with_hi16_in_VGPR_16, -- harmless, but also useless.
Eliminates a few inferred AMDGPU register classes:
- VS_32_with_hi16
- VS_32_Lo256_with_hi16
- VS_32_Lo128_with_hi16
- VRegOrLds_32_and_VS_32_Lo256
- VRegOrLds_32_and_VS_32_Lo128
- SRegOrLds_32_and_VRegOrLds_32
Causes no register class changes for other targets.
81 lines
4.9 KiB
YAML
81 lines
4.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=localstackalloc -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass=localstackalloc -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX12 %s
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---
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name: local_stack_alloc__v_add_u32_e64__literal_offsets
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 4096, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets
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; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
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; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[COPY]]
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; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], 256, 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX10-NEXT: SI_RETURN
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;
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; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets
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; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
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; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
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; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
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; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX12-NEXT: SI_RETURN
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%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, %0
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%1:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, %1
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SI_RETURN
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...
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---
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name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 4096, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
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; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 100
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; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
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; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 156, [[V_ADD_U32_e64_]], 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 412, [[V_ADD_U32_e64_]], 0, implicit $exec
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
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; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[COPY]]
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; GFX10-NEXT: SI_RETURN
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;
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; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
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; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
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; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
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; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
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; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
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; GFX12-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
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; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
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; GFX12-NEXT: SI_RETURN
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%0:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, %0
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%1:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, %1
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%2:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1179657 /* reguse:VGPR_32 */, %2
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SI_RETURN
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...
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