d68d47db7b
This goes through some Arm instructions and adds hasSideEffects = 0 to ones where it was not already implied. This should help with scheduling and instruction movement.
85 lines
2.1 KiB
LLVM
85 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s
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define i32 @sbfx1(i32 %a) {
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; CHECK-LABEL: sbfx1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: sbfx r0, r0, #7, #11
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; CHECK-NEXT: bx lr
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%t1 = lshr i32 %a, 7
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%t2 = trunc i32 %t1 to i11
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%t3 = sext i11 %t2 to i32
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ret i32 %t3
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}
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define i32 @ubfx1(i32 %a) {
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; CHECK-LABEL: ubfx1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ubfx r0, r0, #7, #11
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; CHECK-NEXT: bx lr
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%t1 = lshr i32 %a, 7
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%t2 = trunc i32 %t1 to i11
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%t3 = zext i11 %t2 to i32
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ret i32 %t3
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}
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define i32 @ubfx2(i32 %a) {
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; CHECK-LABEL: ubfx2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ubfx r0, r0, #7, #11
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; CHECK-NEXT: bx lr
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%t1 = lshr i32 %a, 7
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%t2 = and i32 %t1, 2047
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ret i32 %t2
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}
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; rdar://12870177
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define i32 @ubfx_opt(ptr nocapture %ctx, i32 %x) nounwind readonly ssp {
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; CHECK-LABEL: ubfx_opt:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ubfx r3, r1, #16, #8
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; CHECK-NEXT: lsr r2, r1, #24
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; CHECK-NEXT: ubfx r1, r1, #8, #8
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; CHECK-NEXT: ldr r2, [r0, r2, lsl #2]
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; CHECK-NEXT: ldr r3, [r0, r3, lsl #2]
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; CHECK-NEXT: ldr r0, [r0, r1, lsl #2]
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; CHECK-NEXT: add r2, r3, r2
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; CHECK-NEXT: add r0, r2, r0
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; CHECK-NEXT: bx lr
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entry:
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%and = lshr i32 %x, 8
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%shr = and i32 %and, 255
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%and1 = lshr i32 %x, 16
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%shr2 = and i32 %and1, 255
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%shr4 = lshr i32 %x, 24
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%arrayidx = getelementptr inbounds i32, ptr %ctx, i32 %shr4
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%0 = load i32, ptr %arrayidx, align 4
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%arrayidx5 = getelementptr inbounds i32, ptr %ctx, i32 %shr2
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%1 = load i32, ptr %arrayidx5, align 4
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%add = add i32 %1, %0
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%arrayidx6 = getelementptr inbounds i32, ptr %ctx, i32 %shr
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%2 = load i32, ptr %arrayidx6, align 4
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%add7 = add i32 %add, %2
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ret i32 %add7
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}
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define i32 @ubfx3(i32 %a) {
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; CHECK-LABEL: ubfx3:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ubfx r0, r0, #11, #1
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; CHECK-NEXT: bx lr
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%t1 = and i32 %a, 2048
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%t2 = lshr i32 %t1, 11
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ret i32 %t2
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}
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define i32 @ubfx4(i32 %a) {
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; CHECK-LABEL: ubfx4:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ubfx r0, r0, #7, #3
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; CHECK-NEXT: bx lr
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%t1 = and i32 %a, 896
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%t2 = lshr i32 %t1, 7
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ret i32 %t2
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}
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