efcf64e898
See if we can fold all elements of an OR of buildvectors: OR(-1,X) -> -1, OR(0,X) -> X, etc.
73 lines
2.3 KiB
LLVM
73 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
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define <8 x i16> @pr25080(<8 x i32> %a) {
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; LE-LABEL: pr25080:
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; LE: # %bb.0: # %entry
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; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; LE-NEXT: xxlxor 34, 34, 34
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; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; LE-NEXT: lxvd2x 0, 0, 3
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; LE-NEXT: xxland 35, 35, 0
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; LE-NEXT: vcmpequw 2, 3, 2
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; LE-NEXT: mfvsrwz 3, 34
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; LE-NEXT: xxsldwi 0, 34, 34, 1
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; LE-NEXT: xxswapd 1, 34
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; LE-NEXT: xxsldwi 2, 34, 34, 3
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; LE-NEXT: mffprwz 5, 0
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; LE-NEXT: mffprwz 6, 1
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; LE-NEXT: mffprwz 4, 2
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; LE-NEXT: mtvsrd 34, 3
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; LE-NEXT: li 3, -1
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; LE-NEXT: mtvsrd 35, 6
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; LE-NEXT: mtvsrd 36, 5
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; LE-NEXT: vmrghh 3, 4, 3
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; LE-NEXT: mtvsrd 36, 4
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; LE-NEXT: vmrghh 2, 4, 2
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; LE-NEXT: mtvsrd 36, 3
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; LE-NEXT: xxmrglw 0, 34, 35
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; LE-NEXT: vsplth 4, 4, 3
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; LE-NEXT: xxspltw 1, 36, 3
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; LE-NEXT: xxmrgld 34, 0, 1
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; LE-NEXT: blr
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;
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; BE-LABEL: pr25080:
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; BE: # %bb.0: # %entry
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; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; BE-NEXT: xxlxor 34, 34, 34
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; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; BE-NEXT: lxvw4x 0, 0, 3
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; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; BE-NEXT: xxland 35, 35, 0
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; BE-NEXT: vcmpequw 2, 3, 2
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; BE-NEXT: mfvsrwz 4, 34
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; BE-NEXT: mtvsrwz 35, 4
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; BE-NEXT: xxsldwi 0, 34, 34, 1
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; BE-NEXT: xxswapd 1, 34
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; BE-NEXT: mffprwz 5, 0
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; BE-NEXT: mffprwz 6, 1
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; BE-NEXT: xxsldwi 2, 34, 34, 3
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; BE-NEXT: lxvw4x 34, 0, 3
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; BE-NEXT: mffprwz 3, 2
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; BE-NEXT: mtvsrwz 36, 6
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; BE-NEXT: mtvsrwz 37, 5
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; BE-NEXT: vperm 4, 5, 4, 2
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; BE-NEXT: mtvsrwz 37, 3
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; BE-NEXT: li 3, -1
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; BE-NEXT: vperm 2, 5, 3, 2
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; BE-NEXT: mtvsrwz 35, 3
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; BE-NEXT: xxmrghw 0, 34, 36
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; BE-NEXT: vsplth 3, 3, 3
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; BE-NEXT: xxspltw 1, 35, 0
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; BE-NEXT: xxmrghd 34, 1, 0
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; BE-NEXT: blr
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entry:
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%0 = trunc <8 x i32> %a to <8 x i23>
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%1 = icmp eq <8 x i23> %0, zeroinitializer
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%2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
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%3 = sext <8 x i1> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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