2502e3b7ba
Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first class denormal_fpenv attribute. Previously the query for the effective denormal mode involved two string attribute queries with parsing. I'm introducing more uses of this, so it makes sense to convert this to a more efficient encoding. The old representation was also awkward since it was split across two separate attributes. The new encoding just stores the default and float modes as bitfields, largely avoiding the need to consider if the other mode is set. The syntax in the common cases looks like this: `denormal_fpenv(preservesign,preservesign)` `denormal_fpenv(float: preservesign,preservesign)` `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)` I wasn't sure about reusing the float type name instead of adding a new keyword. It's parsed as a type but only accepts float. I'm also debating switching the name to subnormal to match the current preferred IEEE terminology (also used by nofpclass and other contexts). This has a behavior change when using the command flag debug options to set the denormal mode. The behavior of the flag ignored functions with an explicit attribute set, per the default and f32 version. Now that these are one attribute, the flag logic can't distinguish which of the two components were explicitly set on the function. Only one test appeared to rely on this behavior, so I just avoided using the flags in it. This also does not perform all the code cleanups this enables. In particular the attributor handling could be cleaned up. I also guessed at how to support this in MLIR. I followed MemoryEffects as a reference; it appears bitfields are expanded into arguments to attributes, so the representation there is a bit uglier with the 2 2-element fields flattened into 4 arguments.
1027 lines
37 KiB
LLVM
1027 lines
37 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64--linux-gnu -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64--linux-gnu -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64--linux-gnu -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
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declare double @__sqrt_finite(double)
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declare float @__sqrtf_finite(float)
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declare x86_fp80 @__sqrtl_finite(x86_fp80)
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declare float @llvm.sqrt.f32(float)
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
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declare <8 x float> @llvm.sqrt.v8f32(<8 x float>)
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declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
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declare double @llvm.sqrt.f64(double)
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declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
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declare float @llvm.fabs.f32(float)
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare double @llvm.fabs.f64(double)
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define double @finite_f64_no_estimate(double %d) #0 {
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; SSE-LABEL: finite_f64_no_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f64_no_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call double @__sqrt_finite(double %d) #2
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ret double %call
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}
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; No estimates for doubles.
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define double @finite_f64_estimate(double %d) #1 {
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; SSE-LABEL: finite_f64_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f64_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call double @__sqrt_finite(double %d) #2
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ret double %call
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}
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define float @finite_f32_no_estimate(float %f) #0 {
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; SSE-LABEL: finite_f32_no_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f32_no_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call float @__sqrtf_finite(float %f) #2
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ret float %call
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}
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define float @finite_f32_estimate_ieee(float %f) #1 {
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; SSE-LABEL: finite_f32_estimate_ieee:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f32_estimate_ieee:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call float @__sqrtf_finite(float %f) #2
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ret float %call
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}
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define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
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; SSE-LABEL: finite_f32_estimate_ieee_ninf:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f32_estimate_ieee_ninf:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call ninf afn float @__sqrtf_finite(float %f) #2
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ret float %call
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}
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define float @finite_f32_estimate_daz(float %f) #4 {
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; SSE-LABEL: finite_f32_estimate_daz:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f32_estimate_daz:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call float @__sqrtf_finite(float %f) #2
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ret float %call
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}
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define float @finite_f32_estimate_daz_ninf(float %f) #4 {
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; SSE-LABEL: finite_f32_estimate_daz_ninf:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: finite_f32_estimate_daz_ninf:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call ninf afn float @__sqrtf_finite(float %f) #2
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ret float %call
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}
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define x86_fp80 @finite_f80_no_estimate(x86_fp80 %ld) #0 {
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; CHECK-LABEL: finite_f80_no_estimate:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fsqrt
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; CHECK-NEXT: retq
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%call = tail call x86_fp80 @__sqrtl_finite(x86_fp80 %ld) #2
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ret x86_fp80 %call
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}
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; Don't die on the impossible.
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define x86_fp80 @finite_f80_estimate_but_no(x86_fp80 %ld) #1 {
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; CHECK-LABEL: finite_f80_estimate_but_no:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fsqrt
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; CHECK-NEXT: retq
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%call = tail call x86_fp80 @__sqrtl_finite(x86_fp80 %ld) #2
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ret x86_fp80 %call
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}
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; PR34994 - https://bugs.llvm.org/show_bug.cgi?id=34994
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define float @sqrtf_check_denorms(float %x) #3 {
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; SSE-LABEL: sqrtf_check_denorms:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtf_check_denorms:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call float @__sqrtf_finite(float %x) #2
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ret float %call
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}
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define float @sqrtf_check_denorms_ninf(float %x) #3 {
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; SSE-LABEL: sqrtf_check_denorms_ninf:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtf_check_denorms_ninf:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call ninf afn float @__sqrtf_finite(float %x) #2
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ret float %call
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}
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define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 {
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; SSE-LABEL: sqrt_v4f32_check_denorms:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrt_v4f32_check_denorms:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtps %xmm0, %xmm0
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; AVX-NEXT: retq
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%call = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) #2
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ret <4 x float> %call
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}
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define <4 x float> @sqrt_v4f32_check_denorms_ieee_ninf(<4 x float> %x) #7 {
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; SSE-LABEL: sqrt_v4f32_check_denorms_ieee_ninf:
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; SSE: # %bb.0:
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; SSE-NEXT: rsqrtps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: mulps %xmm1, %xmm2
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; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
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; SSE-NEXT: mulps %xmm2, %xmm3
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; SSE-NEXT: mulps %xmm1, %xmm2
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; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
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; SSE-NEXT: mulps %xmm3, %xmm2
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; SSE-NEXT: cmpleps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: sqrt_v4f32_check_denorms_ieee_ninf:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
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; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm2
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; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
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; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vmulps %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; AVX1-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: sqrt_v4f32_check_denorms_ieee_ninf:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vrsqrtps %xmm0, %xmm1
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; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm2
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
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; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
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; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; AVX512-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
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; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%call = tail call fast ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) #2
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ret <4 x float> %call
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}
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define <4 x float> @sqrt_v4f32_check_denorms_dynamic_ninf(<4 x float> %x) #8 {
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; SSE-LABEL: sqrt_v4f32_check_denorms_dynamic_ninf:
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; SSE: # %bb.0:
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; SSE-NEXT: rsqrtps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: mulps %xmm1, %xmm2
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; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
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; SSE-NEXT: mulps %xmm2, %xmm3
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; SSE-NEXT: mulps %xmm1, %xmm2
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; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
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; SSE-NEXT: mulps %xmm3, %xmm2
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; SSE-NEXT: cmpleps %xmm0, %xmm1
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; SSE-NEXT: andps %xmm2, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: sqrt_v4f32_check_denorms_dynamic_ninf:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
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; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm2
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; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
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; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vmulps %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; AVX1-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: sqrt_v4f32_check_denorms_dynamic_ninf:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vrsqrtps %xmm0, %xmm1
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; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm2
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
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; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
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; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
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; AVX512-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
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; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%call = tail call fast ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) #2
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ret <4 x float> %call
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}
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define float @f32_no_estimate(float %x) #0 {
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; SSE-LABEL: f32_no_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm1
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; SSE-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
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; SSE-NEXT: divss %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f32_no_estimate:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
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; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%sqrt = tail call float @llvm.sqrt.f32(float %x)
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%div = fdiv fast float 1.0, %sqrt
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ret float %div
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}
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define float @f32_estimate(float %x) #1 {
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; SSE-LABEL: f32_estimate:
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; SSE: # %bb.0:
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; SSE-NEXT: rsqrtss %xmm0, %xmm1
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; SSE-NEXT: mulss %xmm1, %xmm0
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; SSE-NEXT: mulss %xmm1, %xmm0
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; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: mulss %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: f32_estimate:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
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; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: f32_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
|
|
; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX512-NEXT: vmulss %xmm0, %xmm1, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call float @llvm.sqrt.f32(float %x)
|
|
%div = fdiv fast float 1.0, %sqrt
|
|
ret float %div
|
|
}
|
|
|
|
define float @f32_estimate2(float %x) #5 {
|
|
; SSE-LABEL: f32_estimate2:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtss %xmm0, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: f32_estimate2:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%sqrt = tail call fast float @llvm.sqrt.f32(float %x)
|
|
ret float %sqrt
|
|
}
|
|
|
|
define <4 x float> @v4f32_no_estimate(<4 x float> %x) #0 {
|
|
; SSE-LABEL: v4f32_no_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtps %xmm0, %xmm1
|
|
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; SSE-NEXT: divps %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: v4f32_no_estimate:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtps %xmm0, %xmm0
|
|
; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; AVX-NEXT: vdivps %xmm0, %xmm1, %xmm0
|
|
; AVX-NEXT: retq
|
|
%sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
|
|
%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <4 x float> %div
|
|
}
|
|
|
|
define <4 x float> @v4f32_estimate(<4 x float> %x) #1 {
|
|
; SSE-LABEL: v4f32_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: rsqrtps %xmm0, %xmm1
|
|
; SSE-NEXT: mulps %xmm1, %xmm0
|
|
; SSE-NEXT: mulps %xmm1, %xmm0
|
|
; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
|
|
; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulps %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v4f32_estimate:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
|
|
; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm0, %xmm1, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v4f32_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vrsqrtps %xmm0, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm2 = (xmm1 * xmm0) + xmm2
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm0 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX512-NEXT: vmulps %xmm0, %xmm1, %xmm0
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
|
|
%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <4 x float> %div
|
|
}
|
|
|
|
define <4 x float> @v4f32_estimate2(<4 x float> %x) #5 {
|
|
; SSE-LABEL: v4f32_estimate2:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
|
|
; SSE-NEXT: andps %xmm0, %xmm1
|
|
; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
|
|
; SSE-NEXT: cmpleps %xmm1, %xmm2
|
|
; SSE-NEXT: rsqrtps %xmm0, %xmm1
|
|
; SSE-NEXT: mulps %xmm1, %xmm0
|
|
; SSE-NEXT: andps %xmm2, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v4f32_estimate2:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
|
|
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
|
|
; AVX1-NEXT: vcmpleps %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vrsqrtps %xmm0, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm0, %xmm0
|
|
; AVX1-NEXT: vandps %xmm0, %xmm1, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v4f32_estimate2:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
|
|
; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm1
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
|
|
; AVX512-NEXT: vcmpleps %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vrsqrtps %xmm0, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm0, %xmm0
|
|
; AVX512-NEXT: vandps %xmm0, %xmm1, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
|
|
ret <4 x float> %sqrt
|
|
}
|
|
|
|
define <8 x float> @v8f32_no_estimate(<8 x float> %x) #0 {
|
|
; SSE-LABEL: v8f32_no_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtps %xmm1, %xmm2
|
|
; SSE-NEXT: sqrtps %xmm0, %xmm3
|
|
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; SSE-NEXT: movaps %xmm1, %xmm0
|
|
; SSE-NEXT: divps %xmm3, %xmm0
|
|
; SSE-NEXT: divps %xmm2, %xmm1
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v8f32_no_estimate:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vsqrtps %ymm0, %ymm0
|
|
; AVX1-NEXT: vmovaps {{.*#+}} ymm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; AVX1-NEXT: vdivps %ymm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v8f32_no_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vsqrtps %ymm0, %ymm0
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; AVX512-NEXT: vdivps %ymm0, %ymm1, %ymm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
|
|
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <8 x float> %div
|
|
}
|
|
|
|
define <8 x float> @v8f32_estimate(<8 x float> %x) #1 {
|
|
; SSE-LABEL: v8f32_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: rsqrtps %xmm0, %xmm2
|
|
; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; SSE-NEXT: mulps %xmm2, %xmm0
|
|
; SSE-NEXT: mulps %xmm2, %xmm0
|
|
; SSE-NEXT: mulps %xmm3, %xmm2
|
|
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; SSE-NEXT: addps %xmm4, %xmm0
|
|
; SSE-NEXT: mulps %xmm2, %xmm0
|
|
; SSE-NEXT: rsqrtps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm2, %xmm3
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: addps %xmm4, %xmm1
|
|
; SSE-NEXT: mulps %xmm3, %xmm1
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v8f32_estimate:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vrsqrtps %ymm0, %ymm1
|
|
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
|
|
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
|
|
; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
|
|
; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
|
; AVX1-NEXT: vmulps %ymm0, %ymm1, %ymm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v8f32_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vrsqrtps %ymm0, %ymm1
|
|
; AVX512-NEXT: vmulps %ymm1, %ymm0, %ymm0
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX512-NEXT: vfmadd231ps {{.*#+}} ymm2 = (ymm1 * ymm0) + ymm2
|
|
; AVX512-NEXT: vmulps %ymm3, %ymm1, %ymm0
|
|
; AVX512-NEXT: vmulps %ymm2, %ymm0, %ymm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
|
|
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <8 x float> %div
|
|
}
|
|
|
|
define <16 x float> @v16f32_no_estimate(<16 x float> %x) #0 {
|
|
; SSE-LABEL: v16f32_no_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtps %xmm3, %xmm4
|
|
; SSE-NEXT: sqrtps %xmm2, %xmm5
|
|
; SSE-NEXT: sqrtps %xmm1, %xmm2
|
|
; SSE-NEXT: sqrtps %xmm0, %xmm1
|
|
; SSE-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; SSE-NEXT: movaps %xmm3, %xmm0
|
|
; SSE-NEXT: divps %xmm1, %xmm0
|
|
; SSE-NEXT: movaps %xmm3, %xmm1
|
|
; SSE-NEXT: divps %xmm2, %xmm1
|
|
; SSE-NEXT: movaps %xmm3, %xmm2
|
|
; SSE-NEXT: divps %xmm5, %xmm2
|
|
; SSE-NEXT: divps %xmm4, %xmm3
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v16f32_no_estimate:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vsqrtps %ymm1, %ymm1
|
|
; AVX1-NEXT: vsqrtps %ymm0, %ymm0
|
|
; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; AVX1-NEXT: vdivps %ymm0, %ymm2, %ymm0
|
|
; AVX1-NEXT: vdivps %ymm1, %ymm2, %ymm1
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v16f32_no_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vsqrtps %zmm0, %zmm0
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} zmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
|
; AVX512-NEXT: vdivps %zmm0, %zmm1, %zmm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> %x)
|
|
%div = fdiv fast <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <16 x float> %div
|
|
}
|
|
|
|
define <16 x float> @v16f32_estimate(<16 x float> %x) #1 {
|
|
; SSE-LABEL: v16f32_estimate:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: rsqrtps %xmm0, %xmm6
|
|
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; SSE-NEXT: mulps %xmm6, %xmm0
|
|
; SSE-NEXT: mulps %xmm6, %xmm0
|
|
; SSE-NEXT: mulps %xmm4, %xmm6
|
|
; SSE-NEXT: movaps {{.*#+}} xmm5 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; SSE-NEXT: addps %xmm5, %xmm0
|
|
; SSE-NEXT: mulps %xmm6, %xmm0
|
|
; SSE-NEXT: rsqrtps %xmm1, %xmm6
|
|
; SSE-NEXT: mulps %xmm6, %xmm1
|
|
; SSE-NEXT: mulps %xmm6, %xmm1
|
|
; SSE-NEXT: mulps %xmm4, %xmm6
|
|
; SSE-NEXT: addps %xmm5, %xmm1
|
|
; SSE-NEXT: mulps %xmm6, %xmm1
|
|
; SSE-NEXT: rsqrtps %xmm2, %xmm6
|
|
; SSE-NEXT: mulps %xmm6, %xmm2
|
|
; SSE-NEXT: mulps %xmm6, %xmm2
|
|
; SSE-NEXT: mulps %xmm4, %xmm6
|
|
; SSE-NEXT: addps %xmm5, %xmm2
|
|
; SSE-NEXT: mulps %xmm6, %xmm2
|
|
; SSE-NEXT: rsqrtps %xmm3, %xmm6
|
|
; SSE-NEXT: mulps %xmm6, %xmm4
|
|
; SSE-NEXT: mulps %xmm6, %xmm3
|
|
; SSE-NEXT: mulps %xmm6, %xmm3
|
|
; SSE-NEXT: addps %xmm5, %xmm3
|
|
; SSE-NEXT: mulps %xmm4, %xmm3
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: v16f32_estimate:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vrsqrtps %ymm0, %ymm2
|
|
; AVX1-NEXT: vmovaps {{.*#+}} ymm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm4
|
|
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0
|
|
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0
|
|
; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
|
|
; AVX1-NEXT: vrsqrtps %ymm1, %ymm5
|
|
; AVX1-NEXT: vmulps %ymm0, %ymm4, %ymm0
|
|
; AVX1-NEXT: vmulps %ymm3, %ymm5, %ymm3
|
|
; AVX1-NEXT: vmulps %ymm5, %ymm1, %ymm1
|
|
; AVX1-NEXT: vmulps %ymm5, %ymm1, %ymm1
|
|
; AVX1-NEXT: vaddps %ymm2, %ymm1, %ymm1
|
|
; AVX1-NEXT: vmulps %ymm1, %ymm3, %ymm1
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: v16f32_estimate:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vrsqrt14ps %zmm0, %zmm1
|
|
; AVX512-NEXT: vmulps %zmm1, %zmm0, %zmm0
|
|
; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + mem
|
|
; AVX512-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
|
|
; AVX512-NEXT: vmulps %zmm0, %zmm1, %zmm0
|
|
; AVX512-NEXT: retq
|
|
%sqrt = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> %x)
|
|
%div = fdiv fast <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
|
|
ret <16 x float> %div
|
|
}
|
|
|
|
; x / (fabs(y) * sqrt(z)) --> x * rsqrt(y*y*z)
|
|
|
|
define float @div_sqrt_fabs_f32(float %x, float %y, float %z) {
|
|
; SSE-LABEL: div_sqrt_fabs_f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: mulss %xmm1, %xmm1
|
|
; SSE-NEXT: mulss %xmm2, %xmm1
|
|
; SSE-NEXT: xorps %xmm2, %xmm2
|
|
; SSE-NEXT: rsqrtss %xmm1, %xmm2
|
|
; SSE-NEXT: mulss %xmm2, %xmm1
|
|
; SSE-NEXT: mulss %xmm2, %xmm1
|
|
; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
|
; SSE-NEXT: mulss %xmm2, %xmm0
|
|
; SSE-NEXT: mulss %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: div_sqrt_fabs_f32:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vmulss %xmm1, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm0, %xmm0
|
|
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: div_sqrt_fabs_f32:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm1, %xmm1
|
|
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
|
|
; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX512-NEXT: vmulss %xmm2, %xmm0, %xmm0
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%s = call fast float @llvm.sqrt.f32(float %z)
|
|
%a = call fast float @llvm.fabs.f32(float %y)
|
|
%m = fmul fast float %s, %a
|
|
%d = fdiv fast float %x, %m
|
|
ret float %d
|
|
}
|
|
|
|
; x / (fabs(y) * sqrt(z)) --> x * rsqrt(y*y*z)
|
|
|
|
define <4 x float> @div_sqrt_fabs_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
|
|
; SSE-LABEL: div_sqrt_fabs_v4f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: mulps %xmm1, %xmm1
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: rsqrtps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
|
; SSE-NEXT: mulps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm2, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: div_sqrt_fabs_v4f32:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vrsqrtps %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: div_sqrt_fabs_v4f32:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm1, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vrsqrtps %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
|
|
%a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
|
|
%m = fmul contract reassoc <4 x float> %a, %s
|
|
%d = fdiv contract reassoc arcp <4 x float> %x, %m
|
|
ret <4 x float> %d
|
|
}
|
|
|
|
; This has 'arcp' but does not have 'reassoc' FMF.
|
|
; We allow converting the sqrt to an estimate, but
|
|
; do not pull the divisor into the estimate.
|
|
; x / (fabs(y) * sqrt(z)) --> x * rsqrt(z) / fabs(y)
|
|
|
|
define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
|
|
; SSE-LABEL: div_sqrt_fabs_v4f32_fmf:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: rsqrtps %xmm2, %xmm3
|
|
; SSE-NEXT: mulps %xmm3, %xmm2
|
|
; SSE-NEXT: mulps %xmm3, %xmm2
|
|
; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
|
; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
|
|
; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulps %xmm2, %xmm3
|
|
; SSE-NEXT: divps %xmm1, %xmm3
|
|
; SSE-NEXT: mulps %xmm3, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: div_sqrt_fabs_v4f32_fmf:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vrsqrtps %xmm2, %xmm3
|
|
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
|
|
; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
|
|
; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm3, %xmm2
|
|
; AVX1-NEXT: vdivps %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: div_sqrt_fabs_v4f32_fmf:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vrsqrtps %xmm2, %xmm3
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX512-NEXT: vmulps %xmm4, %xmm3, %xmm4
|
|
; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX512-NEXT: vaddps %xmm3, %xmm2, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm4, %xmm2
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
|
|
; AVX512-NEXT: vandps %xmm3, %xmm1, %xmm1
|
|
; AVX512-NEXT: vdivps %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
|
|
%a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
|
|
%m = fmul <4 x float> %a, %s
|
|
%d = fdiv arcp <4 x float> %x, %m
|
|
ret <4 x float> %d
|
|
}
|
|
|
|
; No estimates for f64, so do not convert fabs into an fmul.
|
|
|
|
define double @div_sqrt_fabs_f64(double %x, double %y, double %z) {
|
|
; SSE-LABEL: div_sqrt_fabs_f64:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: sqrtsd %xmm2, %xmm2
|
|
; SSE-NEXT: mulsd %xmm2, %xmm1
|
|
; SSE-NEXT: divsd %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: div_sqrt_fabs_f64:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX-NEXT: vsqrtsd %xmm2, %xmm2, %xmm2
|
|
; AVX-NEXT: vmulsd %xmm1, %xmm2, %xmm1
|
|
; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%s = call fast double @llvm.sqrt.f64(double %z)
|
|
%a = call fast double @llvm.fabs.f64(double %y)
|
|
%m = fmul fast double %s, %a
|
|
%d = fdiv fast double %x, %m
|
|
ret double %d
|
|
}
|
|
|
|
; This is a special case for the general pattern above -
|
|
; if the sqrt operand is the same as the other mul op,
|
|
; then fabs may be omitted.
|
|
; x / (y * sqrt(y)) --> x * rsqrt(y*y*y)
|
|
|
|
define float @div_sqrt_f32(float %x, float %y) {
|
|
; SSE-LABEL: div_sqrt_f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movaps %xmm1, %xmm2
|
|
; SSE-NEXT: mulss %xmm1, %xmm2
|
|
; SSE-NEXT: mulss %xmm1, %xmm2
|
|
; SSE-NEXT: xorps %xmm1, %xmm1
|
|
; SSE-NEXT: rsqrtss %xmm2, %xmm1
|
|
; SSE-NEXT: mulss %xmm1, %xmm2
|
|
; SSE-NEXT: mulss %xmm1, %xmm2
|
|
; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
|
; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulss %xmm1, %xmm0
|
|
; SSE-NEXT: mulss %xmm2, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: div_sqrt_f32:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vmulss %xmm1, %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulss %xmm2, %xmm0, %xmm0
|
|
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: div_sqrt_f32:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
|
|
; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX512-NEXT: vmulss %xmm2, %xmm0, %xmm0
|
|
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%s = call fast float @llvm.sqrt.f32(float %y)
|
|
%m = fmul fast float %s, %y
|
|
%d = fdiv fast float %x, %m
|
|
ret float %d
|
|
}
|
|
|
|
; This is a special case for the general pattern above -
|
|
; if the sqrt operand is the same as the other mul op,
|
|
; then fabs may be omitted.
|
|
; x / (y * sqrt(y)) --> x * rsqrt(y*y*y)
|
|
|
|
define <4 x float> @div_sqrt_v4f32(<4 x float> %x, <4 x float> %y) {
|
|
; SSE-LABEL: div_sqrt_v4f32:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movaps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm1, %xmm2
|
|
; SSE-NEXT: rsqrtps %xmm2, %xmm1
|
|
; SSE-NEXT: mulps %xmm1, %xmm2
|
|
; SSE-NEXT: mulps %xmm1, %xmm2
|
|
; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
|
; SSE-NEXT: mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: mulps %xmm2, %xmm1
|
|
; SSE-NEXT: mulps %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX1-LABEL: div_sqrt_v4f32:
|
|
; AVX1: # %bb.0:
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vrsqrtps %xmm1, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX1-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
|
; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX1-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: div_sqrt_v4f32:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vrsqrtps %xmm1, %xmm2
|
|
; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
|
|
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
|
|
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
|
|
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; AVX512-NEXT: retq
|
|
%s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %y)
|
|
%m = fmul contract reassoc <4 x float> %y, %s
|
|
%d = fdiv contract reassoc arcp <4 x float> %x, %m
|
|
ret <4 x float> %d
|
|
}
|
|
|
|
define double @sqrt_fdiv_common_operand(double %x) nounwind {
|
|
; SSE-LABEL: sqrt_fdiv_common_operand:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtsd %xmm0, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: sqrt_fdiv_common_operand:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%sqrt = call fast double @llvm.sqrt.f64(double %x)
|
|
%r = fdiv fast double %x, %sqrt
|
|
ret double %r
|
|
}
|
|
|
|
define <2 x double> @sqrt_fdiv_common_operand_vec(<2 x double> %x) nounwind {
|
|
; SSE-LABEL: sqrt_fdiv_common_operand_vec:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtpd %xmm0, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: sqrt_fdiv_common_operand_vec:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtpd %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%sqrt = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
|
|
%r = fdiv arcp nsz reassoc <2 x double> %x, %sqrt
|
|
ret <2 x double> %r
|
|
}
|
|
|
|
define double @sqrt_fdiv_common_operand_extra_use(double %x, ptr %p) nounwind {
|
|
; SSE-LABEL: sqrt_fdiv_common_operand_extra_use:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtsd %xmm0, %xmm0
|
|
; SSE-NEXT: movsd %xmm0, (%rdi)
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: sqrt_fdiv_common_operand_extra_use:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: vmovsd %xmm0, (%rdi)
|
|
; AVX-NEXT: retq
|
|
%sqrt = call fast double @llvm.sqrt.f64(double %x)
|
|
store double %sqrt, ptr %p
|
|
%r = fdiv fast double %x, %sqrt
|
|
ret double %r
|
|
}
|
|
|
|
define double @sqrt_simplify_before_recip(double %x, ptr %p) nounwind {
|
|
; SSE-LABEL: sqrt_simplify_before_recip:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtsd %xmm0, %xmm0
|
|
; SSE-NEXT: movsd {{.*#+}} xmm1 = [1.0E+0,0.0E+0]
|
|
; SSE-NEXT: divsd %xmm0, %xmm1
|
|
; SSE-NEXT: movsd %xmm1, (%rdi)
|
|
; SSE-NEXT: retq
|
|
;
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|
; AVX-LABEL: sqrt_simplify_before_recip:
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|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+0,0.0E+0]
|
|
; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm1
|
|
; AVX-NEXT: vmovsd %xmm1, (%rdi)
|
|
; AVX-NEXT: retq
|
|
%sqrt = tail call fast double @llvm.sqrt.f64(double %x)
|
|
%rsqrt = fdiv fast double 1.0, %sqrt
|
|
%sqrt_fast = fdiv fast double %x, %sqrt
|
|
store double %rsqrt, ptr %p, align 8
|
|
ret double %sqrt_fast
|
|
}
|
|
|
|
define <2 x double> @sqrt_simplify_before_recip_vec(<2 x double> %x, ptr %p) nounwind {
|
|
; SSE-LABEL: sqrt_simplify_before_recip_vec:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtpd %xmm0, %xmm0
|
|
; SSE-NEXT: movapd {{.*#+}} xmm1 = [1.0E+0,1.0E+0]
|
|
; SSE-NEXT: divpd %xmm0, %xmm1
|
|
; SSE-NEXT: movupd %xmm1, (%rdi)
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: sqrt_simplify_before_recip_vec:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtpd %xmm0, %xmm0
|
|
; AVX-NEXT: vmovddup {{.*#+}} xmm1 = [1.0E+0,1.0E+0]
|
|
; AVX-NEXT: # xmm1 = mem[0,0]
|
|
; AVX-NEXT: vdivpd %xmm0, %xmm1, %xmm1
|
|
; AVX-NEXT: vmovupd %xmm1, (%rdi)
|
|
; AVX-NEXT: retq
|
|
%sqrt = tail call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
|
|
%rsqrt = fdiv fast <2 x double> <double 1.0, double 1.0>, %sqrt
|
|
%sqrt_fast = fdiv fast <2 x double> %x, %sqrt
|
|
store <2 x double> %rsqrt, ptr %p, align 8
|
|
ret <2 x double> %sqrt_fast
|
|
}
|
|
|
|
define double @sqrt_simplify_before_recip_order(double %x, ptr %p) nounwind {
|
|
; SSE-LABEL: sqrt_simplify_before_recip_order:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: sqrtsd %xmm0, %xmm0
|
|
; SSE-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
|
|
; SSE-NEXT: divsd %xmm0, %xmm1
|
|
; SSE-NEXT: movsd %xmm1, (%rdi)
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: sqrt_simplify_before_recip_order:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]
|
|
; AVX-NEXT: vdivsd %xmm0, %xmm1, %xmm1
|
|
; AVX-NEXT: vmovsd %xmm1, (%rdi)
|
|
; AVX-NEXT: retq
|
|
%sqrt = tail call fast double @llvm.sqrt.f64(double %x)
|
|
%sqrt_fast = fdiv fast double %x, %sqrt
|
|
%rsqrt = fdiv fast double 42.0, %sqrt
|
|
store double %rsqrt, ptr %p, align 8
|
|
ret double %sqrt_fast
|
|
}
|
|
|
|
attributes #0 = { "reciprocal-estimates"="!sqrtf,!vec-sqrtf,!divf,!vec-divf" }
|
|
attributes #1 = { "reciprocal-estimates"="sqrt,vec-sqrt" }
|
|
attributes #2 = { nounwind readnone }
|
|
attributes #3 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|ieee) }
|
|
attributes #4 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(ieee|preservesign) }
|
|
attributes #5 = { "reciprocal-estimates"="all:0" }
|
|
attributes #6 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|dynamic) }
|
|
|
|
; Attributes without
|
|
; TODO: Merge with previous attributes when this attribute can be deleted.
|
|
attributes #7 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|ieee) } ; #3
|
|
attributes #8 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|dynamic) } ; #6
|